Method of fabricating field effect transistor having polycrystalline silicon gate junction

• US 5,438,007 A
• Filed: 09/28/1993
• Issued: 08/01/1995
• Est. Priority Date: 07/02/1993
• Status: Expired due to Term

• Current Assignee: Thunderbird Technologies Incorporated
• Original Assignee: Thunderbird Technologies Incorporated
• Inventors: Vinal, Albert W., Dennen, Michael W.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): DUTTON, BRIAN KEITH
• Application Number:
  US08/127,767
• Time in Patent Office: 672 Days
• Field of Search: 437/41, 437/46, 437/191, 437/45, 257/412, 257/407, 257/756
• US Class Current: 438/289
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence

Abstract

A field effect transistor includes a polycrystalline silicon gate having a semiconductor junction therein. The semiconductor junction is formed of first and second oppositely doped polycrystalline silicon layers, and extends parallel to the substrate face. The polycrystalline silicon gate including the semiconductor junction therein is perfectly formed by implanting ions into the top of the polycrystalline silicon gate simultaneous with implantation of the source and drain regions. The semiconductor junction thus formed does not adversely impact the performance of the field effect transistor, and provides a low resistance ohmic gate contact. The gate need not be masked during source and drain implant, resulting in simplified fabrication.

Claims

1. A method of forming a field effect transistor comprising the steps of:

providing a semiconductor substrate having an insulating layer on a face thereof;

forming a single polycrystalline silicon layer of first conductivity type on said insulating layer, said single polycrystalline silicon layer including a pair of opposing ends;

simultaneously doping a portion of said single polycrystalline silicon layer, and portions of said semiconductor substrate adjacent said pair of opposing ends, with dopant ions of a second conductivity type, to simultaneously form a semiconductor junction in said single polycrystalline silicon layer extending parallel to said substrate face, and spaced apart source and drain regions in said substrate at said opposing ends of said single polycrystalline silicon layer.

2. The method of claim 1 wherein said forming step comprises the steps of:

forming said single polycrystalline silicon layer on said insulating layer; and

patterning said single polycrystalline silicon layer to form said pair of opposing ends.

3. The method of claim 1 wherein said simultaneously doping step comprises the step of directing ions of said second conductivity type towards said substrate face.

4. The method of claim 3 wherein said single polycrystalline silicon layer is free of a masking layer thereon, during said simultaneously doping step, such that said ions of said second conductivity type enter into said single polycrystalline silicon layer.

5. The method of claim 1 wherein said insulating layer comprises a field oxide portion and a gate oxide portion, and wherein said single polycrystalline silicon layer is formed on said gate oxide portion.

6. The method of claim 1 wherein said single polycrystalline silicon layer forming step is preceded by the step of forming a well of said second conductivity type in said semiconductor substrate, at said substrate face, and wherein said single polycrystalline layer forming step comprises the step of forming said single polycrystalline silicon layer on said insulating layer such that said well extends beyond said first and second opposing ends at said substrate face.

7. The method of claim 1 further comprising the step of forming electrical contacts to said source and drain regions and to said single polycrystalline silicon layer.