Method of fabrication of MOSFET device with buried bit line

• US 5,438,009 A
• Filed: 04/02/1993
• Issued: 08/01/1995
• Est. Priority Date: 04/02/1993
• Status: Expired due to Term

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Yang, Ming-Tzong, Hong, Gary
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): TSAI, H JEY
• Application Number:
  US08/100,307
• Time in Patent Office: 851 Days
• Field of Search: 437/47, 437/52, 437/60, 437/919, 257/304, 257/306-308, 257/311
• US Class Current: 438/253
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor

Abstract

A doped FET DRAM includes a silicon substrate, with a buried bit line in the silicon substrate. A plug extends down through the substrate to the bit line. A source region and a drain region are positioned above the plug in the substrate with one thereof connected to the plug with a layer of gate oxide above the source region and drain region. A gate above the gate oxide is juxtaposed with the source region and drain region. The source is connected to a capacitor formed of two layers of polysilicon separated by a dielectric of an ONO oxide layer.

Claims

1. A method of fabrication of a DRAM MOSFET comprising

a) forming a FOX structure on the surface of a semiconductor substrate, and applying field oxidation,

b) implanting a buried bit line into said substrate,

c) forming a gate oxide onto said substrate,

d) applying polysilicon and etching with a mask,

e) forming source/drain regions in said substrate,

f) forming a doped contact PLUG beneath a first one of said source/drain regions in said substrate said PLUG providing connection between said one source/drain region and said buried bit line, and

g) forming a polysilicon structure connected to a second one of said source/drain regions in said substrate, and

h) forming a polysilicon/ONO/polysilicon capacitor.

2. A method in accordance with claim 1 wherein the dopant in said PLUG is selected from an N+ dopant in the group consisting of phosphorous (P) and arsenic (As) and from a P+ dopant consisting of boron (B) with a dose of between about 1E14 cm^-2 and about 5E16 cm^-2, an energy of between about 100 keV and about 400 keV for P, between about 50 keV and about 300 keV for B, and between about 150 keV and about 700 keV for As in an implanter tool.

3. A method in accordance with claim 1 wherein said ion implantation of said buried bit line is performed employing N+ or P+ dopant implanted in the buried layer, where the N+ dopant is selected from the group consisting of phosphorous (P) and arsenic (As) and where the P+ dopant is selected from the group consisting of boron (B) and gallium (Ga) with a dose of between about 1E14 cm^-2 and about 5E16 cm^-2, an energy of between about 300 keV and about 800 keV for P, between about 100 keV and about 400 keV for B, and between about 800 keV and about 1200 keV for As in an implanter tool.

4. A method in accordance with claim 3 wherein the dopant in said source/drain region is selected from an N+ dopant and a P+ dopant, wherein said N+ dopant is selected from the group consisting of phosphorous (P) and arsenic (As) and where said dopant is a P+ dopant consisting of boron (B) with a dose of between about 1E14 cm^-2 and about 6E16 cm^-2, an energy of between about 10 keV and about 120 keV for P, between about 10 keV and about 120 keV for B, and between about 20 keV and about 120 keV for As in an implanter tool.

5. A method in accordance with claim 1 wherein said buried bit line is implanted to a depth between about 0.2 μ

m and about 2 μ

m.

6. A method in accordance with claim 2 wherein said buried bit line is implanted to a depth between about 0.2 μ

m and about 2 μ

m.

7. A method in accordance with claim 1 wherein said PLUG is implanted with a dopant where when said dopant is N+, said dopant is selected from the group consisting of phosphorous (P) and arsenic (As) and where when said dopant is a P+ dopant comprising boron (B) with a dose of between about 1E14 cm^-2 and about 6E16 cm^-2, an energy of between about 100 and about 400 keV for P, between about 80 keV and about 300 keV for B, and between about 150 keV and about 700 keV for As.

8. A method of fabrication of a DRAM MOSFET on a semiconductor substrate, said method comprising

a) implanting a buried bit line into said semiconductor substrate,

b) forming an epitaxial layer above said buried bit line,

c) forming a FOX structure on the surface of said semiconductor substrate, and performing a field oxidation step,

d) forming a gate oxide onto said substrate,

e) applying polysilicon and etching with a mask,

f) forming source/drain regions in said substrate,

g) forming a doped contact PLUG beneath a first one of said source/drain regions in said substrate, said PLUG providing connection between said one source/drain region and said buried bit line,

h) forming a polysilicon structure connected to a a second one of said source/drain regions on said substrate, and

i) forming a polysilicon/ONO/polysilicon capacitor.

9. A method in accordance with claim 8 wherein the dopant in said PLUG can be an N+ dopant and a P+ dopant wherein the N+ dopant is selected from the group consisting of phosphorous (P) and arsenic (As) and the P+ dopant comprising boron (B) with a dose of between about 1E14 cm^-2 and about 5E16 cm^-2, an energy of between about 100 keV and about 400 keV for P, between about 50 keV and about 300 keV for B, and between about 150 keV and about 700 keV for As in an implanter tool.

10. A method in accordance with claim 8 wherein said ion implantation of said buried bit line is performed employing N+ or P+ dopant implanted in the buried layer, where the N+ dopant is selected from the group consisting of phosphorous (P) and arsenic (As) and where the P+ dopant selected from the group consisting of boron (B) and gallium (Ga) with a dose of between about 1E14 cm^-2 and about 5E16 cm^-2, an energy of between about 300 keV and about 800 keV for P, between about 100 keV and about 400 keV for B, and between about 800 keV and about 1200 keV for As in an implanter tool.

11. A method in accordance with claim 10 wherein when the dopant in said source/drain region is an N+ dopant, it is selected from the group consisting of phosphorous (P) and arsenic (As) and where it dopant is a P+ dopant comprising of boron (B) with a dose of between about 1E14 cm^-2 and about 6E16 cm^-2, an energy of between about 15 keV and about 150 keV for P, between about 10 keV and about 100 keV for B, and between about 40 keV and about 200 keV for As in an implanter tool.

12. A method in accordance with claim 8 wherein said buried bit line is implanted to a depth between about 0.2 μ

m and about 2 μ

m.

13. A method in accordance with claim 9 wherein said buried bit line is implanted to a depth between about 0.2 μ

m and about 2 μ

m.

14. A method in accordance with claim 8 wherein said PLUG is implanted with a dopant where when said dopant is N+, said dopant is selected from the group consisting of phosphorous (P) and arsenic (As) and where when said dopant is a P+ dopant comprising of boron (B) with a dose of between about 1E14 cm^-2 and about 6E16 cm^-2, an energy of between about 100 keV and about 400 keV for P, between about 80 keV and about 300 keV for B, and between about 150 keV and about 700 keV for As.