Digital frequency multiplier utilizing digital controlled oscillator

• US 5,438,300 A
• Filed: 04/01/1994
• Issued: 08/01/1995
• Est. Priority Date: 04/01/1994
• Status: Expired due to Term

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Saban, Rami, Efendovich, Avner, Karpati, Varda
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US08/221,736
• Time in Patent Office: 487 Days
• Field of Search: 331/1 A, 331/10, 331/11, 331/16, 331/17, 331/18, 331/34, 331/57, 360/51, 327/270, 327/276, 327/277, 327/278, 327/279, 327/280, 327/281, 327/282, 327/283, 327/284, 327/105-107, 327/237-253, 327/291-305, 455/260
• US Class Current: 331/16
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A frequency multiplier includes a ring oscillator having a number of logic gates arranged in a plurality of rings. Control inputs enable the selection of individual gates so as to connect them into the ring or, conversely, remove them from the ring. As additional gates are removed, the combined delay imposed by the gates remaining in the ring is reduced and the frequency of the oscillator increases. A variable delay element, preferably a group of tri-state inverters connected in parallel, is connected between two of the gates. The oscillator is fine tuned by controlling the delay inserted by the variable delay element. The frequency multiplier also includes a frequency comparator. A reference frequency is passed through a divide-by-K unit and the output of the ring oscillator is passed through a divide-by-N unit, N being greater than K. The frequency multiplier is coarse-tuned by progressively removing additional gates from the ring oscillator, and then fine-tuned by increasing the delay imposed by the variable delay element. At the conclusion of coarse and fine tuning, the frequency multiplier is locked at a frequency which closely approximates a reference frequency multiplied by N/K. An accuracy of 1% or less may be achieved. When the frequency multiplier ceases to be hooked on a frequency, it enters an idle state in which it consumes no power.

Claims

1. A frequency multiplier comprising:

a control logic unit comprising a divide-by-K unit, a divide-by-N unit and a frequency comparator, respective outputs of said divide-by-K unit and said divide-by-N unit being connected to inputs of said frequency comparator; and

a ring oscillator having an output connected to an input of said divide-by-N unit, said ring oscillator comprising a plurality of coarse delay units connected into a plurality of rings, a different number of said coarse delay units being connected in different ones of said plurality of rings, and a variable delay unit connected in all of said rings, a delay introduced by said variable delay unit being adjustable independently of said coarse delay units.

2. The frequency multiplier of claim 1 wherein said variable delay unit comprises a plurality of delay elements, each of said delay elements being capable of applying a different delay to a signal circulating in any one of said rings.

3. The frequency multiplier of claim 1 wherein said variable delay unit comprises a tri-state inverter.

4. The frequency multiplier of claim 3 wherein said variable delay unit comprises a plurality of tri-state inverters connected in parallel, an input of each tri-state inverter being connected to one of a plurality of outputs of a decoder.

5. The frequency multiplier of claim 4 wherein each of said tri-state inverters imposes a different delay.

6. The frequency multiplier of claim 4 wherein each of said tri-state inverters imposes the same delay.

7. The frequency multiplier of claim 1 wherein at least one of said coarse delay units comprises an AND gate and first and second OR gates, outputs of said first and second OR gates being connected to respective inputs of said AND gate, said first OR gate being connected into a circuit path of a first one of said rings, said second OR gate being connected into a circuit path of a second one of said rings.

8. The frequency multiplier of claim 7 wherein an input of said first OR gate is connected to an output of a decoder, and an input of said second OR gate is connected to said output of said decoder through an inverter.

9. The frequency multiplier of claim 1 further comprising a first decoder having a plurality of outputs, each of said plurality of outputs of said first decoder being connected to an input of one of said coarse delay units.

10. The frequency multiplier of claim 9 further comprising a second decoder having a plurality of outputs, each of said plurality of outputs of said decoder being connected to said variable delay unit.

11. A method of multiplying an input signal having a selected frequency to obtain an output signal having a frequency approximately equal to N/K times said selected frequency, said method comprising;

(a) providing the frequency multiplier of claim 1;

(b) delivering said input signal to an input of said divide-by-K unit;

(c) selecting a ring in said oscillator containing n of said coarse delay units and setting said variable delay unit to have a delay m;

(d) comparing frequencies output by said divide-by-K unit and said divide-by-N unit, respectively, in said frequency comparator;

(e) selecting a ring in said ring oscillator containing fewer than n of said coarse delay units;

(f) repeating step (d);

(g) repeating steps (e) and (f) until said frequency comparator indicates that the frequency output of said divide-by-N unit is greater than the frequency output of said divide-by-K unit;

(h) increasing the delay provided by said variable delay unit;

(i) repeating step (d); and

(j) repeating steps (h) and (i) until said frequency comparator indicates that the frequency output of said divide-by-N unit is lower than the frequency output of said divide-by-K unit.

12. The method of claim 11 wherein said frequency multiplier enters an idle state following step (j), said frequency multiplier consuming no power while in said idle state.

13. The method of claim 1 wherein the frequency output of said ring oscillator following step (j) is within 1% of said selected frequency multiplied by

14. A frequency multiplier comprising:

a control logic unit comprising a divide-by-K unit, a divide-by-N unit and a frequency comparator, respective outputs of said divide-by-K unit and said divide-by-N unit being connected to inputs of said frequency comparator; and

a ring oscillator having an output connected to an input of said divide-by-N unit, said ring oscillator comprising;

a plurality of coarse delay units connected into a plurality of rings, a different number of said coarse delay units being connected in different ones of said plurality of rings, and a variable delay unit connected in all of said rings;

a first decoder connected to said rings, said first decoder for receiving a digital code from said control logic unit and providing an output to select one of said rings; and

a second decoder connected to said variable delay unit, said second decoder for receiving a digital code from said control logic unit and providing an output to control a delay introduced by said variable delay unit.

15. The frequency multiplier of claim 14 wherein said variable delay unit comprises a plurality of delay elements, each of said delay elements capable of applying a different delay to a signal circulating in any one of said rings.

16. The frequency multiplier of claim 15 wherein said delay elements are connected in parallel.

17. The frequency multiplier of claim 15 wherein said variable delay unit comprises a tri-state inverter.