Digital frequency multiplier utilizing digital controlled oscillator
First Claim
1. A frequency multiplier comprising:
- a control logic unit comprising a divide-by-K unit, a divide-by-N unit and a frequency comparator, respective outputs of said divide-by-K unit and said divide-by-N unit being connected to inputs of said frequency comparator; and
a ring oscillator having an output connected to an input of said divide-by-N unit, said ring oscillator comprising a plurality of coarse delay units connected into a plurality of rings, a different number of said coarse delay units being connected in different ones of said plurality of rings, and a variable delay unit connected in all of said rings, a delay introduced by said variable delay unit being adjustable independently of said coarse delay units.
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Accused Products
Abstract
A frequency multiplier includes a ring oscillator having a number of logic gates arranged in a plurality of rings. Control inputs enable the selection of individual gates so as to connect them into the ring or, conversely, remove them from the ring. As additional gates are removed, the combined delay imposed by the gates remaining in the ring is reduced and the frequency of the oscillator increases. A variable delay element, preferably a group of tri-state inverters connected in parallel, is connected between two of the gates. The oscillator is fine tuned by controlling the delay inserted by the variable delay element. The frequency multiplier also includes a frequency comparator. A reference frequency is passed through a divide-by-K unit and the output of the ring oscillator is passed through a divide-by-N unit, N being greater than K. The frequency multiplier is coarse-tuned by progressively removing additional gates from the ring oscillator, and then fine-tuned by increasing the delay imposed by the variable delay element. At the conclusion of coarse and fine tuning, the frequency multiplier is locked at a frequency which closely approximates a reference frequency multiplied by N/K. An accuracy of 1% or less may be achieved. When the frequency multiplier ceases to be hooked on a frequency, it enters an idle state in which it consumes no power.
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Citations
17 Claims
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1. A frequency multiplier comprising:
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a control logic unit comprising a divide-by-K unit, a divide-by-N unit and a frequency comparator, respective outputs of said divide-by-K unit and said divide-by-N unit being connected to inputs of said frequency comparator; and a ring oscillator having an output connected to an input of said divide-by-N unit, said ring oscillator comprising a plurality of coarse delay units connected into a plurality of rings, a different number of said coarse delay units being connected in different ones of said plurality of rings, and a variable delay unit connected in all of said rings, a delay introduced by said variable delay unit being adjustable independently of said coarse delay units. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A frequency multiplier comprising:
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a control logic unit comprising a divide-by-K unit, a divide-by-N unit and a frequency comparator, respective outputs of said divide-by-K unit and said divide-by-N unit being connected to inputs of said frequency comparator; and a ring oscillator having an output connected to an input of said divide-by-N unit, said ring oscillator comprising; a plurality of coarse delay units connected into a plurality of rings, a different number of said coarse delay units being connected in different ones of said plurality of rings, and a variable delay unit connected in all of said rings; a first decoder connected to said rings, said first decoder for receiving a digital code from said control logic unit and providing an output to select one of said rings; and a second decoder connected to said variable delay unit, said second decoder for receiving a digital code from said control logic unit and providing an output to control a delay introduced by said variable delay unit. - View Dependent Claims (15, 16, 17)
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Specification