Modem having a phase corrector and a voltage controlled oscillator implemented using a multi-stage ring oscillator

• US 5,438,301 A
• Filed: 07/25/1994
• Issued: 08/01/1995
• Est. Priority Date: 07/25/1994
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: AT&T Corporation (AT&T, Inc.)
• Inventors: Havens, Joseph H., Montgomery, Robert K.
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US08/280,638
• Time in Patent Office: 372 Days
• Field of Search: 331/45, 331/56, 331/57, 331/60, 331/174, 331/177, 332/103-105, 332/144-148, 332/151, 332/152, 327/105, 327/171, 327/238, 327/254, 327/255, 327/295, 327/298, 333/138, 329/325, 329/336, 329/346, 329/360
• US Class Current: 331/45
• CPC Class Codes: H03B 27/00 Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
• CPC Class Codes: H03C 3/40 using two signal paths the outputs of which have a predetermined phase difference and at least one output being amplitude-modulated
• CPC Class Codes: H04L 27/364 Arrangements for overcoming imperfections in the modulator, e.g. quadrature error or unbalanced I and Q levels

Abstract

A carrier generator circuit for use in a modem employed in a wireless communication system is described. The carrier generator circuit includes a voltage controlled oscillator comprising an N-stage ring oscillator to generate N balanced vectors of equal magnitude and arbitrary phase difference. The carrier generator circuit also includes a phase corrector to add two of the balanced vectors to generate a sum vector and to subtract the two balanced vectors to generate a difference vector. The sum vector and difference vector have a phase difference of 90 degrees. The sum vector represents an I (in-phase) carrier signal component and the difference vector represents a Q (quadrature-phase) carrier signal component. These I and Q carrier signal components can be used to transmit and receive data signals.

Claims

1. A carrier generator circuit for use in a modem employed in a wireless communication system, comprising:

a voltage controlled oscillator comprising an N-stage ring oscillator to generate N balanced vectors of equal magnitude and arbitrary phase difference; and

a phase corrector to add two of said balanced vectors to generate a sum vector and to subtract said two of said balanced vectors to generate a difference vector, said sum vector and difference vector having a phase difference of 90 degrees, said sum vector representing an I (in-phase) carrier signal component and said difference vector representing a Q (quadrature-phase) carrier signal component.

2. The carrier generator circuit of claim 1, wherein N is equal to two.

3. The carrier generator circuit of claim 1, wherein N is equal to an integer value that is greater than two.

4. The carrier generator circuit of claim 1, wherein a first of said N stages of said ring oscillator comprises:

a first gain setting load having a first terminal and a second terminal, a VCC voltage being applied to said first terminal;

a first emitter follower having a base connected to said second terminal, said VCC voltage being applied to a collector of said first emitter follower, a first output vector representing part of one of said balanced vectors being available from an emitter of said first emitter follower; and

a first portion of a current mirror connected to said second terminal to establish a first current flowing through said first gain setting load, said first current establishing a first voltage drop across said first gain setting load, said first output vector having a first magnitude equal to said VCC voltage minus said first voltage drop;

a second of said N stages comprising;

a second gain setting load having a first terminal and a second terminal, said VCC voltage being applied to said second gain setting load first terminal;

a second emitter follower having a base connected to said second gain setting load second terminal, said VCC voltage being applied to a collector of said second emitter follower, a second output vector representing part of another of said balanced vectors being available from an emitter of said second emitter follower; and

a second portion of said current mirror connected to said second gain setting load second terminal to establish a second current substantially equal to said first current flowing through said second gain setting load, said second current establishing a second voltage drop across said second gain setting load, said second gain setting load having a gain setting load value substantially equal to that of said first gain setting load such that said second voltage drop is substantially equal to said first voltage drop, said second output vector having a second magnitude equal to said VCC voltage minus said second voltage drop, said second magnitude being substantially equal to said first magnitude.

5. The carrier generator circuit of claim 4, wherein each of said N stages of said ring oscillator introduces phase delay such that said balanced vectors generated by said ring oscillator are of arbitrary phase difference.

6. The carrier generator circuit of claim 5, wherein said first and second stages of said ring oscillator each comprises an emitter coupled pair, a base of said emitter coupled pair in said second stage connected to said emitter of said first emitter follower in said first stage, a collector of said emitter coupled pair in said second stage connected to said base of said emitter follower in said second stage, such that phase delay introduced by said second stage is equal to signal propagation delay from said base of said emitter coupled pair in said second stage to said emitter of said emitter follower in said second stage.

7. The carrier generator circuit of claim 1, wherein said phase corrector includes N identical stages, each stage of said phase corrector connected to a stage of said ring oscillator, such that said stages of said ring oscillator are identically loaded.

8. The carrier generator circuit of claim 7, wherein a first stage of said phase corrector comprises:

first and second emitter coupled pairs, said first and second emitter coupled pairs both receiving a first vector and an inverted first vector, said first vector and said inverted first vector representing one of said balanced vectors;

a second stage of said phase corrector comprising;

third and fourth emitter coupled pairs, said third and fourth emitter coupled pairs both receiving a second vector and an inverted second vector, said second vector and said inverted second vector representing another of said balanced vectors;

wherein a collector of a transistor forming part of said first emitter coupled pair, having a base connected to said first vector, being connected at a first common collector point to a collector of a transistor forming part of said fourth emitter coupled pair, having a base connected to said inverted second vector, a first output vector resulting from an addition of said inverted second vector and said first vector being available from said first common collector point, said first output vector representing a part of said difference vector; and

a collector of a transistor forming part of said second emitter coupled pair, having a base connected to said first vector, being connected at a second common collector point to a collector of a transistor forming part of said third emitter coupled pair, having a base connected to said second vector, a second output vector resulting from adding said first vector to said second vector being available from said second common collector point, said second output vector representing a part of said sum vector.

9. A modulator for use in a modem employed in a wireless communication system, comprising:

a voltage controlled oscillator comprising an N-stage ring oscillator to generate N balanced vectors of equal magnitude and arbitrary phase difference;

a phase corrector to add two of said balanced vectors to generate a sum vector and to subtract said two of said balanced vectors to generate a difference vector, said sum vector and difference vector having a phase difference of 90 degrees, said sum vector representing an I (in-phase) carrier signal component and said difference vector representing a Q (quadrature-phase) carrier signal component; and

means for modulating said I and Q carrier signal components using I and Q data signals, respectively.

10. The modulator of claim 9, wherein a first of said N stages of said ring oscillator comprises:

a first gain setting load having a first terminal and a second terminal, a VCC voltage being applied to said first terminal;

a first emitter follower having a base connected to said second terminal, said VCC voltage being applied to a collector of said first emitter follower, a first output vector representing part of one of said balanced vectors being available from an emitter of said first emitter follower; and

a first portion of a current mirror connected to said second terminal to establish a first current flowing through said first gain setting load, said first current establishing a first voltage drop across said first gain setting load, said first output vector having a first magnitude equal to said VCC voltage minus said first voltage drop;

a second of said N stages comprising;

a second gain setting load having a first terminal and a second terminal, said VCC voltage being applied to said second gain setting load first terminal;

a second emitter follower having a base connected to said second gain setting load second terminal, said VCC voltage being applied to a collector of said second emitter follower, a second output vector representing part of another of said balanced vectors being available from an emitter of said second emitter follower; and

a second portion of said current mirror connected to said second gain setting load second terminal to establish a second current substantially equal to said first current flowing through said second gain setting load, said second current establishing a second voltage drop across said second gain setting load, said second gain setting load having a gain setting load value substantially equal to that of said first gain setting load such that said second voltage drop is substantially equal to said first voltage drop, said second output vector having a second magnitude equal to said VCC voltage minus said second voltage drop, said second magnitude being substantially equal to said first magnitude.

11. The modulator of claim 10, wherein each of said N stages of said ring oscillator introduces phase delay such that said balanced vectors generated by said ring oscillator are of arbitrary phase difference.

12. The modulator of claim 11, wherein said first and second stages of said ring oscillator each comprises an emitter coupled pair, a base of said emitter coupled pair in said second stage connected to said emitter of said first emitter follower in said first stage, a collector of said emitter coupled pair in said second stage connected to said base of said emitter follower in said second stage, such that phase delay introduced by said second stage is equal to signal propagation delay from said base of said emitter coupled pair in said second stage to said emitter of said emitter follower in said second stage.

13. The modulator of claim 9, wherein said phase corrector includes N identical stages, each stage of said phase corrector connected to a stage of said ring oscillator, such that said stages of said ring oscillator are identically loaded.

14. The modulator of claim 13, wherein a first stage of said phase corrector comprises:

first and second emitter coupled pairs, said first and second emitter coupled pairs both receiving a first vector and an inverted first vector, said first vector and said inverted first vector representing one of said balanced vectors;

a second stage of said phase corrector comprising;

third and fourth emitter coupled pairs, said third and fourth emitter coupled pairs both receiving a second vector and an inverted second vector, said second vector and said inverted second vector representing another of said balanced vectors;

wherein a collector of a transistor forming part of said first emitter coupled pair, having a base connected to said first vector, being connected at a first common collector point to a collector of a transistor forming part of said fourth emitter coupled pair, having a base connected to said inverted second vector, a first output vector resulting from an addition of said inverted second vector and said first vector being available from said first common collector point, said first output vector representing a part of said difference vector; and

a collector of a transistor forming part of said second emitter coupled pair, having a base connected to said first vector, being connected at a second common collector point to a collector of a transistor forming part of said third emitter coupled pair, having a base connected to said second vector, a second output vector resulting from adding said first vector to said second vector being available from said second common collector point, said second output vector representing a part of said sum vector.

15. A demodulator for use in a modem employed in a wireless communication system, comprising:

a voltage controlled oscillator comprising an N-stage ring oscillator to generate N balanced vectors of equal magnitude and arbitrary phase difference;

a phase corrector to add two of said balanced vectors to generate a sum vector and to subtract said two of said balanced vectors to generate a difference vector, said sum vector and difference vector having a phase difference of 90 degrees, said sum vector representing an I (in-phase) carrier signal component and said difference vector representing a Q (quadrature-phase) carrier signal component; and

means for demodulating modulated I and Q carrier components using said I and Q carrier signal components.

16. The demodulator of claim 15, wherein a first of said N stages of said ring oscillator comprises:

a first gain setting load having a first terminal and a second terminal, a VCC voltage being applied to said first terminal;

a first emitter follower having a base connected to said second terminal, said VCC voltage being applied to a collector of said first emitter follower, a first output vector representing part of one of said balanced vectors being available from an emitter of said first emitter follower; and

a first portion of a current mirror connected to said second terminal to establish a first current flowing through said first gain setting load, said first current establishing a first voltage drop across said first gain setting load, said first output vector having a first magnitude equal to said VCC voltage minus said first voltage drop;

a second of said N stages comprising;

a second gain setting load having a first terminal and a second terminal, said VCC voltage being applied to said second gain setting load first terminal;

a second emitter follower having a base connected to said second gain setting load second terminal, said VCC voltage being applied to a collector of said second emitter follower, a second output vector representing part of another of said balanced vectors being available from an emitter of said second emitter follower; and

a second portion of said current mirror connected to said second gain setting load second terminal to establish a second current substantially equal to said first current flowing through said second gain setting load, said second current establishing a second voltage drop across said second gain setting load, said second gain setting load having a gain setting load value substantially equal to that of said first gain setting load such that said second voltage drop is substantially equal to said first voltage drop, said second output vector having a second magnitude equal to said VCC voltage minus said second voltage drop, said second magnitude being substantially equal to said first magnitude.

17. The demodulator of claim 16, wherein each of said N stages of said ring oscillator introduces phase delay such that said balanced vectors generated by said ring oscillator are of arbitrary phase difference.

18. The demodulator of claim 17, wherein said first and second stages of said ring oscillator each comprises an emitter coupled pair, a base of said emitter coupled pair in said second stage connected to said emitter of said first emitter follower in said first stage, a collector of said emitter coupled pair in said second stage connected to said base of said emitter follower in said second stage, such that phase delay introduced by said second stage is equal to signal propagation delay from said base of said emitter coupled pair in said second stage to said emitter of said emitter follower in said second stage.

19. The demodulator of claim 15, wherein said phase corrector includes N identical stages, each stage of said phase corrector connected to a stage of said ring oscillator, such that said stages of said ring oscillator are identically loaded.

20. The demodulator of claim 19, wherein a first stage of said phase corrector comprises:

first and second emitter coupled pairs, said first and second emitter coupled pairs both receiving a first vector and an inverted first vector, said first vector and said inverted first vector representing one of said balanced vectors;

a second stage of said phase corrector comprising;

third and fourth emitter coupled pairs, said third and fourth emitter coupled pairs both receiving a second vector and an inverted second vector, said second vector and said inverted second vector representing another of said balanced vectors;

wherein a collector of a transistor forming part of said first emitter coupled pair, having a base connected to said first vector, being connected at a first common collector point to a collector of a transistor forming part of said fourth emitter coupled pair, having a base connected to said inverted second vector, a first output vector resulting from an addition of said inverted second vector and said first vector being available from said first common collector point, said first output vector representing a part of said difference vector; and

a collector of a transistor forming part of said second emitter coupled pair, having a base connected to said first vector, being connected at a second common collector point to a collector of a transistor forming part of said third emitter coupled pair, having a base connected to said second vector, a second output vector resulting from adding said first vector to said second vector being available from said second common collector point, said second output vector representing a part of said sum vector.