Flash EEPROM array data and header file structure

• US 5,438,573 A
• Filed: 06/01/1994
• Issued: 08/01/1995
• Est. Priority Date: 09/13/1991
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SunDisk Corporation (Seagate Technology Holdings Plc), Western Digital Corporation
• Inventors: Albert, Richard, Gupta, Anil, Mangan, John S., Craig, Jeffrey, Norman, Robert D., Lofgren, Karl M. J., Stai, Jeffrey D.
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US08/252,052
• Time in Patent Office: 426 Days
• Field of Search: 371/10.3
• US Class Current: 714/711
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 29/765 in solid state disks

Abstract

A file structure employed in a flash electrically erasable and programmable read only memory ("EEPROM") system and aspects of forming and using certain data fields within such a file structure. An array of rows and columns of EEPROM memory cells is divided into blocks of cells that are separately addressable for the purpose of erasing an entire block of cells at the same time. Each block contains several rows of cells with certain columns thereof storing a sector of data, typically 512 bytes of data, and other columns of cells within the same rows being used as spare cells to replace any defective sector data cells and store overhead (header) information about the block and the data sector. Such overhead information includes pointers to locations of any defective sector data cells within the block, whether the block has been mapped out in favor of another block, error correction codes for the sector data and the header information, and other similar types of information.

Claims

1. A method of utilizing an array of flash EEPROM cells organized into word line rows and bit line columns with cells interposed thereinbetween, such that each cell is addressable by a row and a column, comprising the steps of:

dividing said array into a plurality of blocks having unique block addresses for the purpose of simultaneously erasing all of the cells in an addressed block, and individually including cells addressable within a plurality of adjacent rows and a plurality of consecutive columns,

designating, within individual blocks,

a plurality of header cells addressable within said plurality of adjacent rows and a first portion of said plurality of consecutive columns of said block, such that if a column defect affecting one of said plurality of consecutive columns of said block exists, then said first portion is designated such that said affected one column is not within said first portion, and

a plurality of data cells addressable within said plurality of adjacent rows and a remaining portion of said plurality of consecutive columns of said block,

designating, within said plurality of header cells, a certain number of bad data bit pointer cells for storing addresses of any defective cells within said plurality of data cells, and a certain number of spare data cells for storing data redirected from said plurality of data cells as a result of any defective cells within said plurality of data cells, and

storing, within individual blocks, addresses of any defective cells within said plurality of data cells, into said bad data bit pointer cells within said plurality of header cells, and

storing, within individual blocks, data into said plurality of data cells and a number of spare data cells determined by the number of any defective cells within said plurality of data cells.

2. The method as recited in claim 1, wherein said data storing step comprises the steps of, within each row of said plurality of adjacent rows, sequentially storing data into said plurality of data cells starting from a first column in said plurality of consecutive columns towards a last column in said plurality of consecutive columns, while skipping columns designated for said plurality of header cells and skipping any defective cells within said plurality of data cells, and thence, sequentially storing data into the number of spare data cells within said plurality of header cells on the row.

3. The method as recited in claim 2, wherein said sequentially storing data into said plurality of data cells step comprises the steps of:

comparing an address stored in one of said bad data bit pointer cells against a next address corresponding to one of said plurality of data cells, and

storing data into the data cell corresponding to said next address and incrementing said next address, if said bad data bit pointer cell address does not equal said next address, or incrementing said next address without storing data into the data cell corresponding to said next address, if said bad data bit pointer cell address does equal said next address.

4. The method as recited in claim 2, further comprising the step of designating, within said plurality of header cells, a certain number of error correction code cells, wherein said data storing step further comprises, after sequentially storing data into a row of said plurality of adjacent rows, the steps of calculating an error correction code number for the row of data and storing said calculated error correction code number into a portion of said error correction code cells corresponding to the row of data.

5. The method as recited in claim 4, further comprising the steps of:

reading data stored in a row of the plurality of adjacent rows within an individual block,

comparing the data read from said row with an error correction code number stored in a portion of said error correction code cells corresponding to said row, and

attempting a correction of said row of data if the data read from said row does not compare with the error correction code number stored in said portion of said error correction code cells corresponding to said row.

6. The method as recited in claim 5, wherein said reading data step comprises the steps of sequentially reading data within said row, starting from a first column in said plurality of consecutive columns towards a last column in said plurality of consecutive columns, while skipping columns designated for said plurality of header cells and skipping any defective cells within said plurality of data cells, and thence, sequentially reading data from a number of spare data cells determined by the number of any defective cells within said plurality of data cells.

7. The method as recited in claim 1, further comprising the steps of:

designating, within said plurality of header cells, a field of cells for storing a count of the number of times that the block including said plurality of header cells has been erased,

transferring the contents of said plurality of header cells into a buffer memory,

erasing the block including said plurality of header cells, and

storing an incremented count of the number of times that the block including said plurality of header cells has been erased, into said field of cells for storing a count of the number of times that the block including said plurality of header cells has been erased.

8. The method as recited in claim 1, further comprising the steps of:

designating, within said plurality of header cells, a field of cells for storing the value of a last erase voltage used for erasing the block including said plurality of header cells,

erasing the block including said plurality of header cells by applying an erase voltage to the cells of said block, and

storing the value of said erase voltage into said field of cells.

9. A method of utilizing an array of flash EEPROM cells organized into word line rows and bit line columns with cells interposed thereinbetween, such that each cell is addressable by a row and a column, comprising said steps of:

dividing said array into a plurality of blocks individually including cells addressable within a plurality of adjacent rows and a plurality of consecutive columns, and having unique block addresses for said purpose of simultaneously erasing all of said cells in an addressed block,

designating, within individual blocks,

a first plurality of header cells addressable within said plurality of adjacent rows and a first portion of said plurality of consecutive columns of said block, such that if a column defect affecting one of said plurality of consecutive columns of said block exists, then said first portion is designated such that said affected one column is not within said first portion,

a second plurality of header cells addressable within said plurality of adjacent rows and a second portion of said plurality of consecutive columns of said block, such that if a column defect affecting one of said plurality of consecutive columns of said block exists, then said second portion is designated such that said affected one column is not within said second portion, and

a plurality of data cells addressable within said plurality of adjacent rows and a remaining portion of said plurality of consecutive columns of said block,

designating, within said first plurality of header cells, a certain number of bad header bit pointer cells for storing addresses of any defective cells within said first plurality of header cells, a certain number of bad data bit pointer cells for storing addresses of any defective cells within said plurality of data cells, and a certain number of spare header cells addressable within the last row of said plurality of adjacent rows and the last columns of said first portion of said plurality of consecutive columns,

designating, within said second plurality of header cells, a certain number of spare data cells for storing data redirected from said plurality of data cells as a result of any defective cells within said plurality of data cells,

storing, within individual blocks, addresses of any defective cells within said first plurality of header cells, into said bad header bit pointer cells of said first plurality of header cells, and addresses of any defective cells within said plurality of data cells, into said bad data bit pointer cells of said second plurality of header cells, and

storing, within individual blocks, data into said plurality of data cells and a number of spare data cells determined by the number of any defective cells within said plurality of data cells.

10. The method as recited in claim 9, further comprising, before said data storing step, the step of sequentially reading row-by-row from said first plurality of header cells starting with a first row of said plurality of adjacent rows by reading from a first column of said first portion of said plurality of consecutive columns to a last column of said first portion of said plurality of consecutive columns, and ending with a last row of said plurality of adjacent rows by reading from a first column of said first portion of said plurality of consecutive columns to a column of one of said spare header cells determined by the number of any defective cells within said first plurality of header cells, while skipping any defective cells within said first plurality of header cells.

11. The method as recited in claim 10, wherein said first plurality of header cells sequentially reading step comprises the steps of:

comparing an address stored in one of said bad header bit pointer cells in said first plurality of header cells, against a next address corresponding to one of said first plurality of header cells, and

reading data from the cell corresponding to said next address and incrementing said next address, if said bad header bit pointer cell address does not equal said next address, or incrementing said next address without reading data from the cell corresponding to said next address, if said bad header bit pointer cell address does equal said next address.

12. The method as recited in claim 10, further comprising the steps of:

designating, within said first plurality of header cells, a certain number of error correction code cells,

calculating, after said storing steps for said defective cell addresses within said first plurality of header cells and within said plurality of data cells, an error correction code number for said first plurality of header cells, and

storing said calculated error correction code number for said first plurality of header cells into said error correction code cells within said first plurality of cells.

13. The method as recited in claim 12, further comprising the steps of:

reading information stored in said first plurality of header cells within an individual block,

comparing the information read from said first plurality of header cells with an error correction code number stored in said error correction code cells of said first plurality of header cells, and

attempting a correction of the read information if the information read from said first plurality of header cells does not compare with the error correction code number stored in said error correction code cells of said first plurality of header cells.

14. In an array of EEPROM cells organized into word line rows and bit line columns with cells interposed thereinbetween, individually addressable by designating a row and a column, and arranged in a plurality of non-overlapping blocks, wherein said plurality of non-overlapping blocks are individually formed of a plurality of successive columns in a plurality of adjacent rows of cells, and accessible by unique block addresses for the purpose of simultaneously erasing all of the cells in an addressed block, said array of EEPROM cells including a file structure within individual blocks which minimizes the effects of any column defects within its individual block, said file structure comprising:

a header file having a plurality of cells addressable within said plurality of adjacent rows and a first portion of said plurality of successive columns of said block, wherein said first portion of columns is selected so as not to include a column defect, and

a plurality of data cells addressable within said plurality of adjacent rows and a remaining portion of said plurality of successive columns of said block, wherein data is stored in said plurality of data cells, and information about said data is stored in said plurality of header cells.

15. The memory block file structure as recited in claim 14, wherein said header file has a first header file including a plurality of spare data cells in each of said plurality of adjacent rows, wherein the spare data cells in each row include data redirected from said plurality of data cells as a result of one or more of said plurality of data cells in the row being defective.

16. The memory block file structure as recited in claim 15, wherein said first header file includes a plurality of ECC cells in each of said plurality of adjacent rows, wherein the ECC cells in each row includes an ECC calculated for data stored in the block row.

17. The memory block file structure as recited in claim 15, wherein said header file has a second header file including a plurality of bad data bit pointer cells, wherein the bad data bit pointer cells include addresses of defective cells in said plurality of data cells.

18. The memory block file structure as recited in claim 17, wherein said second header file includes a plurality of bad header bit pointer cells, wherein the bad header bit pointer cells include addresses of defective cells in said second header file.

19. The memory block file structure as recited in claim 18, wherein said second header file includes a plurality of spare header cells in successive columns including a last column in said last row of said adjacent rows of said second header file, wherein the spare header cells include information redirected from other columns on said last row of said adjacent rows, as a result of one or more of said second header file cells being defective.

20. The memory block file structure as recited in claim 17, wherein said second header file includes a count of the number of times that its block has been erased.

21. The memory block file structure as recited in claim 17, wherein said second header file includes a field designating a suitable erase voltage for its block.

22. The memory block file structure as recited in claim 17, wherein said second header file includes a field containing at least one error correction code calculated from the contents of at least some of the second header file.