Process for DRAM incorporating a high-energy, oblique P-type implant for both field isolation and punchthrough

• US 5,439,835 A
• Filed: 10/14/1994
• Issued: 08/08/1995
• Est. Priority Date: 11/12/1993
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Semiconductor, Inc. (Micron Technology, Inc.)
• Inventors: Gonzalez, Fernando
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US08/324,277
• Time in Patent Office: 298 Days
• Field of Search: 437/35, 437/52, 437/60, 437/919, 437/44, 437/27
• US Class Current: 438/241
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

This invention is a process for fabricating a CMOS dynamic random access memory (DRAM) wherein a high-energy, oblique P-type implant is employed for punchthrough protection and field isolation enhancement or alternatively for punchthrough protection and as the sole field isolation implant. The process proceeds by forming P-type and N-type regions in a silicon substrate, performing an optional field isolation implant and forming field isolation regions using LOCOS or a modified LOCOS sequence, forming a gate dielectric layer, forming wordlines, depositing an offsetting dielectric layer, performing a low-dosage N-type implant in N-channel source/drain regions, forming spacers on the sidewalls of the gate electrodes, constructing cell capacitors superjacent the storage-node regions, performing a high-energy oblique implant with a P-type impurity which penetrates the spacers and field oxide layers, and performing a high-dosage N-type implant in bitline contact regions. As an option, the angle of the P-type oblique implant is varied through a given range to create an anti-punchthrough halo having a graded density. As a further option, a lower energy oblique implant may be performed with an N-type implant to create a graded junction for bitline junction region.

Claims

1. A process for fabricating a dynamic random access memory cell array on a P-type substrate, each cell of said array having a field-effect access transistor that is insulated from neighboring access transistors by a surrounding field isolation layer, each access transistor having a first source/drain region which functions as a bitline contact region, a second source/drain region which functions as a storage node, a channel region between said first and second source/drain regions, and a gate electrode having vertical sidewalls adjacent said first and second source/drain regions, said gate electrode being dielectrically insulated from and overlying said channel region, said process comprising the following steps:

(a) depositing an offsetting dielectric layer which conformally coats said vertical sidewalls;

(b) performing a low-dosage N-type implant in N-channel source/drain regions;

(c) constructing cell capacitors superjacent the storage-node regions;

(d) forming spacers on the sidewalls of the gate electrodes;

(e) performing a high-energy oblique implant with a P-type impurity which penetrates the spacers and field oxide layers;

(f) performing a thermal drive-in step; and

(g) performing a high-dosage N-type source/drain implant in bitline contact regions.

2. The process of claim 1, wherein the impurity for the high-energy oblique P-type implant is boron.

3. The process of claim 2, wherein the high-energy oblique P-type implant is performed with an energy of 50 to 90 Kev and at a dosage level of 1E12 to 1E14.

4. The process of claim 3, wherein the high-energy oblique P-type implant is performed at an incident angle within a range of 25 to 45 degrees from normal to the substrate.

5. The process of claim 4, wherein each transistor gate comprises a portion of a wordline which traverses the array, each wordline having a pair of lateral edges, and the oblique P-type implant is performed by implanting P-type ions obliquely in two directions, each of said directions being oriented such that the P-type ions are implanted in the substrate beneath a lateral edge on each side of the wordline.

6. The process of claim 1, wherein an oblique implant is performed with an N-type impurity to create a graded junction for the bitline contact region between step (f) and step (g).

7. The process of claim 6, wherein the oblique N-type implant impurity is arsenic.

8. The process of claim 7, wherein the oblique N-type implant is performed at an energy of 80 to 120 Kev and at a dosage of within a range of 1E13 to 1E15.

9. The process of claim 8, wherein the oblique N-type implant is performed at an angle within a range of 35 to 55 degrees from normal to the substrate.

10. The process of claim 9, wherein each transistor gate comprises a portion of a wordline which traverses the array, each wordline having a pair of lateral edges, and the oblique P-type implant is performed by implanting P-type ions obliquely in two directions, each of said directions being oriented such that the P-type ions are implanted in the substrate beneath a lateral edge on each side of the wordline.

11. The process of claim 1, wherein an oblique implant is performed with an N-type impurity to create a graded junction for the bitline contact region following step (g).

12. The process of claim 11, wherein the oblique N-type implant impurity is arsenic.

13. The process of claim 12, wherein the oblique N-type implant is performed at an energy of 80 to 120 Kev and at a dosage of within a range of 1E13 to 1E15.

14. The process of claim 13, wherein the oblique N-type implant is performed at an angle within a range of 35 to 55 degrees from normal to the substrate.

15. The process of claim 14, wherein each transistor gate comprises a portion of a wordline which traverses the array, each wordline having a pair of lateral edges, and the oblique P-type implant is performed by implanting P-type ions obliquely in two directions, each of said directions being oriented such that the P-type ions are implanted in the substrate beneath a lateral edge on each side of the wordline.