×

Electrically programmable memory device with improved dual floating gates

  • US 5,440,158 A
  • Filed: 07/05/1994
  • Issued: 08/08/1995
  • Est. Priority Date: 07/05/1994
  • Status: Expired due to Term
First Claim
Patent Images

1. The method of fabricating an improved erasable programmable read only memory device, having dual sidewall float gates comprising:

  • forming a thin insulating layer on the surface of a monocrystalline silicon semiconductor substrate having a background impurity of a first conductivity type;

    depositing a layer of oxidation resistant material over the thin insulating layer;

    patterning the oxidation resistant masking layer to form openings that define field oxide areas on the substrate;

    forming thick field oxide regions in the exposed areas in the substrate adjacent to the surface;

    depositing, exposing, and developing a resist layer on the substrate surface to cover at least a central area between the field oxide regions;

    removing the portions of the oxidation resistant masking layer not covered by the resist layer forming an oxidation resistant masking line with vertical sidewalls;

    removing the resist layer;

    implanting first conductivity type impurity ions into the substrate using the masking line and the field oxide as masks forming first doped regions for threshold voltage adjustment;

    removing the exposed thin insulating layer;

    forming a tunnel oxide layer on the substrate surface;

    depositing a first conformal polycrystalline silicon layer over the substrate;

    anisotropically etching the first conformal polycrystalline silicon layer forming dual floating gates on the vertical sidewalls of the oxidation resistant masking line;

    obliquely ion implanting impurity ions of a first conductivity type into said substrate utilizing the dual floating gates, field oxide regions and masking line as masks forming second doped regions in the substrate located on either side of the floating gate structures;

    removing the oxidation resistant masking line leaving the dual spaced floating gates;

    ion implanting second conductivity type impurity ions into said substrate utilizing the dual floating gates as masks to form a central source region located between the floating gate structures and two spaced drain regions in the substrate located on either side of the floating gate structures;

    thickening said tunnel oxide layer forming a thick insulation layer;

    forming a composite layer over the surface of the substrate;

    depositing a second polycrystalline silicon layer over the composite layer;

    forming a polycide layer on top of the second polycrystalline silicon layer;

    etching the polycide layer, the second polycide layer, the composite layer and the floating gates to form wordlines in the second polycrystalline silicon and polycide layers;

    and forming electrical contacts and metallurgy lines with appropriate passivation, and connecting the source, drain and gate elements to form an erasable programmable memory device.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×