Differential/coherent digital demodulator operating at multiple symbol points

• US 5,440,265 A
• Filed: 09/14/1994
• Issued: 08/08/1995
• Est. Priority Date: 09/14/1994
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures I LLC (Intellectual Ventures LLC)
• Original Assignee: SiCOM, Inc. (Renesas Electronics Corporation)
• Inventors: Garvey, Brendan J., McCallister, Ronald D., Cochran, Bruce A.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US08/306,112
• Time in Patent Office: 328 Days
• Field of Search: 329/300, 329/304, 329/341, 375/80, 375/111, 375/113
• US Class Current: 329/300
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 1/20 using signal quality detector
• CPC Class Codes: H04L 27/22 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 7/046 using a dotting sequence

Abstract

Symbols (18) of a burst (12) are sub-divided into symbol sections (20). Each symbol section (20) is sampled and converted into polar coordinates. A buffer bank (38) selectably delays the samples and replays a preamble (14). A demod bank (40) includes a coherent demod (58) and several differential demods (60). Each differential demod (60) processes its own stream of symbol sections (20). The differential demods (60) feed a preamble detector (66) and a symbol synchronization circuit (62). The symbol synchronization circuit (62) identifies the symbol section (20) which yields the smallest magnitude of frequency errors. This symbol section (20) is processed by the coherent demod (58) to acquire carrier phase and recover data. The coherent demod (58) is implemented in the phase domain so that only oscillation signal phase data need be generated in phase locked loops. Two phase locked loops (110, 112) operate in parallel but with initial reference phase offsets so that at least one of the two loops will not experience hang-up.

Claims

1. A coherent digital demodulator for recovering data conveyed by an incoming signal in a stream of symbols, said demodulator comprising:

a phase angle generator configured to generate a phase value for each symbol, said phase value defining a phase relationship between in-phase and quadrature components of said incoming signal;

a phase error compensator for generating an adjusted phase angle for each symbol, said phase error compensator having a first input coupled to said phase angle generator, a second input, and an output; and

an integrator, having an input coupled to said phase error compensator output and having an output coupled to said second input of said phase error compensator, for forming a carrier phase tracking loop.

2. A coherent digital demodulator as claimed in claim 1 additionally comprising:

a frequency offset detector having an input coupled to said phase error compensator output and having an output;

a phase offset detector having an input coupled to said phase error compensator and having an output; and

combining means, having a first input coupled to said frequency offset detector, a second input coupled to said phase offset detector, and an output coupled to said integrator input.

3. A coherent digital demodulator as claimed in claim 1 additionally comprising:

a data detector having an input coupled to said phase error compensator output and having an output; and

a phase error detector having a first input coupled to said phase error compensator, a second input coupled to said data detector output, and an output coupled to said input of said integrator.

4. A coherent digital demodulator as claimed in claim 1 additionally comprising:

an alternate phase error compensator for generating an alternate adjusted phase angle for each symbol, said alternate phase error compensator having a first input coupled to said phase angle generator, a second input, and an output;

a phase error offset generator having an input coupled to said alternate phase error compensator and having an output; and

an alternate integrator, having an input coupled to said phase error offset generator output and having an output coupled to said second input of said alternate phase error compensator, for forming an offset carrier phase tracking loop.

5. A coherent digital demodulator as claimed in claim 4 additionally comprising means, coupled to said integrator and to said alternate integrator, for selecting one of said phase error compensator and said alternate phase error compensator to recover said data.

6. A coherent digital demodulator as claimed in claim 1 additionally comprising a symbol synchronizer, coupled to said phase angle generator, for recovering symbol timing from said incoming signal.

7. A coherent digital demodulator as claimed in claim 6 wherein said phase angle generator generates a plurality of phase values for each symbol, each of said plurality of phase values being generated to characterize said incoming signal at a distinct symbol section thereof, and said symbol synchronizer comprises:

a first differential demodulator having an input coupled to said phase angle generator, having an output, and being configured to generate first frequency errors detected at first sections of said symbols;

a second differential demodulator having an input coupled to said phase angle generator, having an output, and being configured to generate second frequency errors detected at second sections of said symbols; and

comparison means, coupled to said outputs of said first and second differential demodulators, for identifying whether frequency errors detected at said first sections are smaller than frequency errors detected at said second sections.

8. A coherent digital demodulator as claimed in claim 7 wherein:

said symbol synchronizer additionally comprises a third differential demodulator having an input coupled to said phase angle generator, having an output, and being configured to generate third frequency errors detected at third sections of said symbols;

said comparison means couples to said output of said third differential demodulator and identifies which of said first, second, and third sections yields the smallest frequency errors; and

said coherent digital demodulator additionally comprises means, coupled to said first, second, and third differential demodulators, for reducing the smallest of said frequency errors detected at said first, second, and third sections.

9. A coherent digital demodulator as claimed in claim 8 wherein said reducing means is configured to adjust timing for the one of said first, second, and third sections that yields the smallest frequency error toward the one of said other sections which yields the next smallest frequency error.

10. A coherent digital demodulator as claimed in claim 7 additionally comprising a symbol section router, having a selection input coupled to said comparison means, data inputs coupled to said phase angle generator, and an output coupled to said phase error compensator, said symbol section router being configured to route phase values associated with the one of said sections having the smallest of said frequency errors to said phase error compensator.

11. A coherent digital demodulator as claimed in claim 1 additionally comprising:

a delay circuit coupled between said phase angle generator and said phase error compensator; and

a preamble detector coupled to said phase angle generator.

12. A coherent digital demodulator as claimed in claim 1 wherein said phase error compensator is a subtraction circuit.

13. A coherent digital demodulator for rapidly acquiring carrier phase synchronization comprising:

a first phase error compensator having a first input adapted to receive an incoming signal, having a second input, and having an output;

a second phase error compensator having a first input adapted to receive said incoming signal, having a second input, and having an output;

a first phase error detector having an input coupled to said first phase error compensator output and having an output coupled to said second input of said first phase error compensator;

a second phase error detector having an input coupled to said second phase error compensator output and having an output; and

a phase error offset generator having an input coupled to said second phase error detector output and having an output coupled to said second input of said second phase error compensator.

14. A coherent digital demodulator as claimed in claim 13 wherein said incoming signal conveys data in a stream of symbols, and said demodulator additionally comprises:

a phase angle generator coupled to said first inputs of said first and second phase error compensators, said phase angle generator being configured to translate said incoming signal into a phase angle value for each symbol, said phase angle value defining a phase relationship between in-phase and quadrature components of said incoming signal;

a first integrator, coupled between said first phase error detector and said second input of said first phase error compensator; and

a second integrator, coupled between said second phase error detector and said second input of said second phase error compensator.

15. A coherent digital demodulator as claimed in claim 14 additionally comprising:

a frequency offset detector having an input coupled to said first phase error detector output and having an output;

a phase offset detector having an input coupled to said first phase error detector output and having an output; and

combining means, having a first input coupled to said frequency offset detector, a second input coupled to said phase offset detector, and an output coupled to said first integrator.

16. A coherent digital demodulator as claimed in claim 13 wherein said incoming signal conveys data in a stream of symbols, and said demodulator additionally comprises means, coupled to said first and second phase error compensators, for selecting one of said first and second phase error compensators to recover said data.

17. A coherent digital demodulator as claimed in claim 13 wherein said incoming signal conveys data in a stream of symbols, and said coherent digital demodulator additionally comprising a symbol synchronizer, coupled to said first inputs of said first and second phase error compensators, for recovering symbol timing from said incoming signal.

18. A coherent digital demodulator as claimed in claim 17 additionally comprising a phase angle generator coupled to said first inputs of said first and second phase error compensators, said phase angle generator being configured to translate said incoming signal into a plurality of phase values for each symbol, said phase values characterizing a phase relationship between in-phase and quadrature components of said incoming signal at a plurality of distinct symbol sections thereof, and wherein said symbol synchronizer comprises:

a first differential demodulator having an input coupled to said phase angle generator, having an output, and being configured to generate first frequency errors detected at first sections of said symbols;

a second differential demodulator having an input coupled to said phase angle generator, having an output, and being configured to generate second frequency errors detected at second sections of said symbols; and

comparison means, coupled to said outputs of said first and second differential demodulators, for identifying whether frequency errors detected at said first sections are smaller than frequency errors detected at said second sections.

19. A coherent digital demodulator as claimed in claim 18 additionally comprising a symbol section router having a selection input coupled to said comparison means, data inputs coupled to said phase angle generator, and an output coupled to said first inputs of said first and second phase error compensators, said symbol section router being configured to route phase values associated with the one of said sections yielding the smaller of said frequency errors to said first and second phase error compensators.

20. A coherent digital demodulator as claimed in claim 13 wherein said incoming signal conveys data in a stream of symbols, and said demodulator additionally comprises:

a digitizer configured to translate said incoming signal into samples which, for each symbol, characterize in-phase and quadrature components of said incoming signal;

a preamble detector coupled to said digitizer; and

a delay circuit coupled between said digitizer and said first inputs of said first and second phase error compensators.

21. A demodulator for demodulating a burst communication signal having a preamble portion followed by conveyed data, said demodulator comprising:

a digitizer for characterizing a parameter of said communication signal which is manipulated to convey data, said digitizer having an output;

a delay circuit having an input coupled to said digitizer output and having an output;

a preamble detector coupled to said digitizer output; and

a symbol synchronizer coupled to said delay circuit output.

22. A demodulator as claimed in claim 21 wherein said delay circuit is configured as a first in, first out (FIFO) memory.

23. A demodulator as claimed in claim 21 wherein said delay circuit is a memory capable of recording at least said preamble portion of said burst communication signal.

24. A demodulator as claimed in claim 21 wherein said delay circuit is a first delay circuit, and said demodulator additionally comprises:

a second delay circuit having an input coupled to said first delay circuit output and having an output; and

a carrier phase acquisition circuit coupled to said second delay circuit output.

25. A demodulator as claimed in claim 24 wherein said signal conveys data in a stream of symbols, said digitizer is a phase angle generator configured to generate a phase value for each symbol, said phase value defining a phase relationship between in-phase and quadrature components of said incoming signal, and said carrier phase acquisition circuit comprises:

a phase error compensator for generating an adjusted phase angle for each symbol, said phase error compensator having a first input coupled to said second delay circuit output, a second input, and an output; and

an integrator, having an input coupled to said-phase error compensator output and having an output coupled to said second input of said phase error compensator, for forming a carrier phase tracking loop.

26. A demodulator as claimed in claim 25 wherein said phase error compensator is a subtraction circuit.

27. A demodulator as claimed in claim 25 additionally comprising:

an alternate phase error compensator for generating an alternate adjusted phase angle for each symbol, said alternate phase error compensator having a first input coupled to said second delay circuit output, a second input, and an output;

a phase error offset generator having an input coupled to said alternate phase error compensator output and having an output;

an alternate integrator, having an input coupled to said phase error offset generator output and having an output coupled to said second input of said alternate phase error compensator, for forming an offset carrier phase tracking loop; and

means, coupled to said integrator and to said alternate integrator, for selecting one of said phase error compensator and said alternate phase error compensator to recover said data.

28. A demodulator as claimed in claim 21 wherein said signal conveys data in a stream of symbols, and said symbol synchronizer comprises:

a first differential demodulator having an input coupled to said delay circuit output, having an output, and being configured to generate first frequency errors detected at first sections of said symbols;

a second differential demodulator having an input coupled to said delay circuit output, having an output, and being configured to generate second frequency errors detected at second sections of said symbols; and

comparison means, coupled to said outputs of said first and second differential demodulators, for identifying whether frequency errors detected at said first symbol sections are smaller than frequency errors detected at said second symbol sections.

29. A method for acquiring an incoming signal that conveys data through a stream of symbols, said method comprising the steps of:

detecting first and second frequency errors for a plurality of symbols, said first and second frequency errors being detected for first and second sections of each symbol, respectively;

identifying whether said frequency errors detected at said first sections are smaller than frequency errors detected at said second sections; and

synchronizing symbol timing in response to said identifying step.

30. A method as claimed in claim 29 wherein said detecting step also detects third frequency errors for said plurality of symbols, said third frequency errors being detected at third sections of each symbol, said identifying step determines which of said first, second, and third sections yields the smallest frequency errors, and said method additionally comprises the steps of:

continuing said detecting step after said synchronizing step; and

reducing frequency errors for the one of said first, second, and third sections which has the smallest frequency error, said reducing step being responsive to frequency errors for the others of said sections.

31. A method as claimed in claim 30 wherein said reducing step comprises the step of adjusting symbol timing for said one of said sections which has the smallest frequency error toward the one of said sections which has the next smallest frequency error.

32. A method as claimed in claim 29 wherein said detecting step comprises the steps of:

differentially demodulating said incoming signal as defined during said first sections; and

differentially demodulating said incoming signal as defined during said second sections.

33. A method as claimed in claim 29 additionally comprising, prior to said detecting step, the steps of:

generating samples which characterize said incoming signal during said first sections and during said second sections;

recording said samples;

monitoring said samples to detect a preamble, said monitoring step occurring during said recording step; and

replaying said recorded samples after said preamble has been detected to produce replayed samples so that said detecting step operates on said replayed samples.

34. A method as claimed in claim 29 additionally comprising, after said synchronizing step, the step of coherently demodulating said incoming signal characterized in the one of said first and second sections which exhibits smaller frequency errors.

35. A method as claimed in claim 34 wherein said coherently demodulating step comprises the step of phase synchronizing first and second adaptive frequency references to said incoming signal as characterized in the one of said first and second sections which exhibits smaller frequency errors, said first and second adaptive frequency references initially being out of phase with one another.

36. A method as claimed in claim 34 wherein said coherently demodulating step comprises the step of operating a phase locked loop using only polar coordinates to track phase of said incoming signal.