Method for handling error information between channel unit and central computer

• US 5,440,729 A
• Filed: 12/02/1994
• Issued: 08/08/1995
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Tanimichi, Tatsuhiko, Kimura, Toshio
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Decady, Albert
• Application Number:
  US08/353,373
• Time in Patent Office: 249 Days
• Field of Search: 395/575, 371/12, 371/47.1, 371/48, 364/265, 364/265.2
• US Class Current: 714/5.11
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers

Abstract

A channel unit is provided between a central computer and a peripheral and includes a plurality of registers for data transfer therebetween. In the event that an error occurs in one of the registers, a processor provided in the channel unit terminates a normal data transfer operation and freezes all the registers. A content of each of the freezed registers is stored, as the error information, into a memory which is provided in the channel unit. The central computer is advised of the error occurrence and issues a reset signal which releases the freezing of the registers. The channel unit receives an instruction, from the central computer, for transferring the error information stored in the memory. The error information stored in the memory is transferred to the central computer, via a data channel, in response to the instruction applied.

Claims

1. A method for transferring error information from one of a plurality of channel units to a central computer if an error occurs in said one of said channel units, said channel units being provided between said central computer and a plurality of respective peripherals and each of said channel units including a plurality of registers for transferring data therebetween via a respective data channel, said method comprising the steps of:

(a) detecting said error which occurred in one of the registers, by a processor provided in said one of said channel units;

(b) interrupting a data transfer operation of said processor in response to the detection of the error and bringing the registers into a freezing mode, thereby rendering said one of said channel units temporarily inoperative without rendering an other channel units inoperative;

(c) acquiring a content of each of the registers, as the error information, into a memory means provided in said one of said channel units, and advising the central computer of the error occurrence;

(d) receiving a first reset signal in said one of said channel units from the central computer and releasing the freezing mode;

(e) receiving an instruction in said one of said channel units, from said central computer, for transferring the error information stored in said memory means;

(f) transferring the error information stored in said memory means to the central computer, via said respective data channel, in response to the instruction received at step (e); and

(g) receiving a second reset signal in said one of said channel units from said central computer at said one of said channel units and rendering said one of said channel units operative in a normal data transfer mode.

2. A method as claimed in claim 1, further comprising the step of:

moving the error information into a data transfer section for use in the data transfer operation before step (f).

3. A method as claimed in claim 2, wherein said data transfer section includes a data buffer into which the error information is stored.

4. A method for transferring error information from one of a plurality of channel units to a central computer if an error occurs in said one of said channel units, said channel units being provided between said central computer and a plurality of respective peripherals and each of said channel units including a plurality of registers for transferring data therebetween via a respective data channel, said method comprising the steps of:

(a) issuing an interrupt signal if said error occurs in one of the registers of said one of said channel units;

(b) applying said interrupt signal to a processor provided in said one of said channel units;

(c) interrupting a data transfer operation of said processor in response to an application of said interrupt signal to said processor;

(d) bringing the registers into a freezing mode, thereby rendering said one of said channel units temporarily inoperative without rendering the other channel units inoperative;

(e) acquiring a content of each of the registers, as an error information, into a memory means provided in said one of said channel units;

(f) advising the central computer of an error occurrence;

(g) receiving a first reset signal in said one of said channel units from the central computer and releasing the freezing mode;

(h) receiving an instruction in said one of said channel units, from said central computer, for transferring the error information stored in said memory means;

(i) transferring the error information stored in said memory means to the central computer, via said respective data channel, in response to the instruction received at step (h); and

(j) receiving a second reset signal in said one of said channel units from the central computer at said one of said channel units and rendering said one of said channel units operative in a normal data transfer mode.

5. A method as claimed in claim 4, further comprising the step of:

moving the error information into a data transfer section for use in a data transfer operation before step (a).

6. A method as claimed in claim 5, wherein said data transfer section includes a data buffer into which the error information is stored.

7. An apparatus for transferring error information to a central computer if an error is detected, said apparatus being provided as one of a plurality of apparatuses between said central computer and a respective plurality of peripherals for transferring data therebetween via a respective data channel, said apparatus comprising:

(a) a plurality of registers;

(b) a processor detecting said error which occurred in one of the registers;

(c) means for interrupting a data transfer operation of said processor in response to the detection of the error, and bringing the registers into a freezing mode, thereby rendering the apparatus temporarily inoperative without rendering the other apparatuses inoperative;

(d) memory means for acquiring a content of each of the registers, as an error information, and advising the central computer of the error occurrence;

(e) means for receiving a first reset signal from the central computer, and for transferring the error information stored in said memory means;

(f) means for receiving an instruction, from said central computer, for transferring the error information stored in said memory means;

(g) means for transferring the error information stored in said memory means to the central computer, via said respective data channel, in response to the instruction; and

(h) means for receiving a second reset signal and for rendering said apparatus operative in a normal data transfer mode in response to a second reset signal applied from said central computer.

8. An apparatus as claimed in claim 7, further comprising a data transfer section and means for moving the error information into said data transfer section for use in a data transfer operation.

9. An apparatus as claimed in claim 8, wherein said data transfer section includes a data buffer into which the error information is stored.

10. An apparatus for transferring error information to a central computer if an error occurs, said apparatus being provided as one of a plurality of apparatuses between said central computer and a respective plurality of peripherals for transferring data therebetween via a respective data channel, said apparatus comprising:

(a) a plurality of registers;

(b) means for issuing an interrupt signal if said error occurs in one of the registers;

(c) means for applying said interrupt signal to a processor, thereby rendering the apparatus temporarily inoperative without rendering the other apparatuses inoperative;

(d) means for interrupting a data transfer operation of said processor in response to an application of said interrupt signal to said processor;

(e) means for bringing the registers into a freezing mode;

(f) memory means for acquiring a content of each of the registers, as an error information;

(g) means for advising the central computer of the error occurrence;

(h) means for receiving a first reset signal from the central computer and releasing the freezing mode;

(i) means for receiving an instruction, from said central computer, for transferring the error information stored in said memory means;

(j) means for transferring the error information stored in the memory means to the central computer, via said respective data channel, in response to the instruction; and

(k) means for receiving a second reset signal from the central computer and rendering said apparatus operative in a normal data transfer mode.

11. An apparatus as claimed in claim 10, further comprising a data transfer section and means for moving the error information into a data transfer section for use in a data transfer operation.

12. An apparatus as claimed in claim 11, wherein said data transfer section includes a data buffer into which the error information is stored.