Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU
First Claim
1. In a multiprocessor system having a plurality of microprocessors, each of said microprocessors having a cache, a memory port, and an input/output unit (IOU), a memory control unit (MCU) in each of said microprocessors comprising:
- a switch network;
a cache interface circuit;
means for coupling said cache interface circuit between said cache and said switch network;
an I/O interface circuit;
means for coupling said I/O interface circuit between said IOU and said switch network;
a memory port interface circuit;
means for coupling said memory port interface circuit between said memory port and said switch network;
switch arbitration means for arbitrating for said switch network;
port arbitration means for arbitrating for said memory port;
means for transferring to said port arbitration means a request to transfer data between one of said cache and said IOU and said memory port through said switch network and said port interface circuit;
means for transferring a port available signal from said port arbitration means to said switch arbitration means when said port interface circuit is free to process said request; and
means responsive to said port available signal for transferring a switch available signal from said switch arbitration means to the source of said request and to said port arbitration means when said switch network is free to process said request whereby data is enabled to be transferred between said one of said cache and said IOU and said memory port.
3 Assignments
0 Petitions
Accused Products
Abstract
A computer system comprising a microprocessor architecture capable of supporting multiple processors. Data transfers between data and instruction caches, I/O devices, and a memory am handled using a switch network. Access to memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes. A test and set bypass circuit is provided for preventing a loss of memory bandwidth due to spin-locking. A row match comparison circuit is provided for reducing memory latency by giving an increased priority to successive requests for access to memory locations having the same row address. Dynamic switch/port arbitration is provided by changing device priority based on the intrinsic priority of the device, the number of times that a request has been serviced based on a row match, the number of times that a device has been denied service, and the number of times that a device has been serviced.
164 Citations
35 Claims
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1. In a multiprocessor system having a plurality of microprocessors, each of said microprocessors having a cache, a memory port, and an input/output unit (IOU), a memory control unit (MCU) in each of said microprocessors comprising:
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a switch network; a cache interface circuit; means for coupling said cache interface circuit between said cache and said switch network; an I/O interface circuit; means for coupling said I/O interface circuit between said IOU and said switch network; a memory port interface circuit; means for coupling said memory port interface circuit between said memory port and said switch network; switch arbitration means for arbitrating for said switch network; port arbitration means for arbitrating for said memory port; means for transferring to said port arbitration means a request to transfer data between one of said cache and said IOU and said memory port through said switch network and said port interface circuit; means for transferring a port available signal from said port arbitration means to said switch arbitration means when said port interface circuit is free to process said request; and means responsive to said port available signal for transferring a switch available signal from said switch arbitration means to the source of said request and to said port arbitration means when said switch network is free to process said request whereby data is enabled to be transferred between said one of said cache and said IOU and said memory port. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A method of transferring data in a multiprocessor architecture capable of supporting a plurality of microprocessors, each of said microprocessors having a cache, a memory port, an input/output unit (IOU) and a memory control unit (MCU), said MCU having a switch network, a cache interface circuit, means for coupling said cache interface circuit between said cache and said switch network, an I/O interface circuit, means for coupling said I/O interface circuit between said IOU and said switch network, a memory port interface circuit, means for coupling said memory port interface circuit between said memory port and said switch network, switch arbitration means for arbitrating for said switch network and port arbitration means for arbitrating for said memory port, comprising the steps of:
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transferring to said port arbitration means a request to transfer data between one of said cache and said IOU and said memory port through said switch network and said port interface circuit; transferring a port available signal from said port arbitration means to said switch arbitration means when said port interface circuit is free to process said request; and transferring a switch available signal from said switch arbitration means to the source of said request and to said port arbitration means when said switch network is free to process said request whereby data is enabled to be transferred between said one of said cache and said IOU and said memory port. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35)
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Specification