Computer system with a processor-direct universal bus connector and interchangeable bus translator
First Claim
1. A computer comprising:
- a microprocessor subsystem module, wherein said microprocessor subsystem module further comprises;
a central processor unit (cpu) having cpu address signal lines, cpu data signal lines and cpu control signal lines which form a central processor unit protocol independent superset of processor-direct signal lines wherein a subset of said superset of processor-direct signal lines includes cpu address signal lines, CPU data address signal lines and cpu control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol;
a memory section coupled to said central processor unit; and
a microprocessor subsystem module processor direct multi-line connector which is in direct electrical communication with said central processor unit superset of processor-direct signal lines; and
a bus translator subsystem adapted for electrical connection to said microprocessor subsystem module via said microprocessor subsystem module processor direct multi-line connector, wherein said bus translator subsystem further comprises;
a bus translator subsystem processor direct multi-line connector which mates with said microprocessor subsystem module processor direct multi-line connector for communicating with said microprocessor subsystem module through said central processor unit protocol independent superset of processor-direct signal lines; and
a first expansion bus which communicates with said central processor unit and said memory section according to said first expansion bus protocol via said bus translator subsytem processor direct multi-line connector.
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Accused Products
Abstract
A universal processor-direct bus structure on a specifically partitioned motherboard uses a separate local bus translator card to adapt to a specific local bus protocol and configuration. The processor-direct bus on the motherboard contains a superset of all of the primary signals required to implement any desired local bus structure. The translator card incorporates the connectors and bus translation protocol for a specific local bus structure on a separate card which is connected to the partitioned motherboard through the universal processor-direct bus. Thus, the universal processor-direct bus combined with the translator card makes it possible to have a standard bus (for example an ISA (Industry Standard Architecture) bus, EISA bus, MCA bus, PCI bus, C-bus, S-100 bus and/or other buses) mounted directly on the motherboard with one or more of the same standard buses or a different local bus interfaced to the motherboard through the universal processor-direct bus. This unique combination of a motherboard having a universal processor-direct bus with plug in local bus translator cards provides a unique, low cost, flexible solution to the problem of standard and local bus obsolescence, local bus non-upgradeability and local bus non-flexibility.
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Citations
13 Claims
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1. A computer comprising:
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a microprocessor subsystem module, wherein said microprocessor subsystem module further comprises; a central processor unit (cpu) having cpu address signal lines, cpu data signal lines and cpu control signal lines which form a central processor unit protocol independent superset of processor-direct signal lines wherein a subset of said superset of processor-direct signal lines includes cpu address signal lines, CPU data address signal lines and cpu control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol; a memory section coupled to said central processor unit; and a microprocessor subsystem module processor direct multi-line connector which is in direct electrical communication with said central processor unit superset of processor-direct signal lines; and a bus translator subsystem adapted for electrical connection to said microprocessor subsystem module via said microprocessor subsystem module processor direct multi-line connector, wherein said bus translator subsystem further comprises; a bus translator subsystem processor direct multi-line connector which mates with said microprocessor subsystem module processor direct multi-line connector for communicating with said microprocessor subsystem module through said central processor unit protocol independent superset of processor-direct signal lines; and a first expansion bus which communicates with said central processor unit and said memory section according to said first expansion bus protocol via said bus translator subsytem processor direct multi-line connector. - View Dependent Claims (2, 3, 4)
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5. A computer system comprising:
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a central processor unit (cpu) having cpu address signal lines, cpu data signal lines and cpu control signal lines which form a central processor unit protocol independent superset of processor-direct signal lines wherein a subset of said superset of processor-direct signal lines includes cpu address signal lines, cpu data signal lines and cpu control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol, said first expansion bus protocol further comprising any one of a VESA local bus protocol or INTEL PCI local bus protocol; a memory section coupled to said central processor unit; a cpu processor direct multi-line connector which is in direct electrical communication with said central processor unit protocol independent superset of processor-direct signal lines; and
a bus translator, said bus translator comprising;a bus translator processor direct multi-line connector which mates with said cpu processor direct multi-line connector for communicating with said central processor unit through said central processor unit protocol independent superset of processor-direct signal lines; and a first expansion bus which communicates with said central processor unit and said memory section according to said first expansion bus protocol via said bus translator processor direct multi-line connector. - View Dependent Claims (6, 7)
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8. A computer system comprising:
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a microprocessor subsystem, wherein said microprocessor subsystem further comprises; a central processor unit (cpu) having cpu address signal lines, cpu data signal lines and cpu control signal lines which form a central processor unit superset of processor-direct signal lines wherein a subset of said superset of processor-direct signal lines includes cpu address signal lines, CPU data signal lines and cpu control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol; a memory section in communication with said central processor unit; and a microprocessor subsystem processor direct multi-line connector which is in direct electrical communication with said central processor unit superset of processor-direct signal lines; and a bus translator subsystem adapted for electrical connection to said microprocessor subsystem via said microprocessor subsystem processor direct multi-line connector, wherein said bus translator subsystem further comprises; a bus translator subsystem processor direct multi-line connector which mates with said microprocessor subsystem processor direct multi-line connector for communicating with said microprocessor subsystem through said central processor unit superset of processor-direct signal lines; a first expansion bus which communicates with said central processor unit and said memory section according to said first expansion bus protocol via said bus translator subsytem processor direct multi-line connector; a second expansion bus which communicates with said central processor unit and said memory section according to a second predetermined expansion bus protocol comprising any one of an ISA bus protocol, EISA bus protocol, MCA bus protocol, PCI bus protocol, C-bus protocol or S-100 bus protocol.
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9. A computer system comprising:
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a central processor unit (cpu) having cpu address signal lines, cpu data signal lines and cpu control signal lines which form a central processor unit superset of processor-direct signal lines wherein a subset of said superset of processor-direct signal lines includes cpu address signal lines, CPU data signal lines and cpu control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol; a memory section in communication with said central processor unit; a cpu processor direct multi-line connector which is in direct electrical communication with said central processor unit superset of processor-direct signal lines; a bus translator comprising; a bus translator processor direct multi-line connector which mates with said cpu processor direct multi-line connector for communicating with said central processor unit through said central processor unit superset of processor-direct signal lines; and a first expansion bus which communicates with said central processor unit and said memory section according to said first expansion bus protocol via said bus translator processor direct multi-line connector; and a second expansion bus which communicates with said central processor unit and said memory section according to a second predetermined expansion bus protocol comprising any one of an ISA bus protocol, EISA bus protocol, MCA bus protocol, PCI bus protocol, C-bus protocol or S-100 bus protocol.
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10. A bus translator comprising:
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a bus translator processor direct multi-line connector adapted for connection to a central processor unit (CPU) protocol independent superset of processor-direct signal lines wherein said CPU protocol independent superset of processor-direct signals includes CPU address signal lines, CPU data signal lines and CPU control lines such that a subset of said protocol independent superset of processor-direct signal lines includes CPU address signal lines, CPU data signal lines and CPU control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol; a first expansion bus which communicates with said central processor unit according to said first expansion bus protocol via said bus translator processor direct multi-line connector wherein said first expansion bus protocol comprises any one of a VESA local bus protocol or INTEL PCI local bus protocol; and a second expansion bus which communicates with said central processor unit according to a second predetermined expansion bus. - View Dependent Claims (11)
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12. A bus translator comprising;
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a bus translator processor direct multi-line connector adapted for connection to a central processor unit (CPU) superset of processor-direct signal lines wherein said CPU superset of processor-direct signal lines includes CPU address signal lines, CPU data signal lines and CPU control signal lines such that a subset of said superset of processor-direct signal lines includes CPU address signal lines, CPU data signal lines and CPU control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol; a first expansion bus which communicates with said central processor unit according to said first expansion bus protocol via said bus translator processor direct multi-line connector; a second expansion bus which communicates with said central processor unit according to a second predetermined expansion bus protocol comprising any one of an ISA bus protocol, EISA bus protocol, MCA bus protocol, PCI bus protocol, C-bus protocol or S-100 bus protocol.
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13. A method of changing the expansion bus protocol on a computer comprising:
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providing a connection to a central processor unit (CPU) protocol independent superset of processor-direct signal lines wherein said CPU protocol independent superset of processor-direct signal lines includes CPU address signal lines, CPU data signal lines and CPU control signal lines such that a subset of said protocol independent superset of processor-direct signal lines includes CPU address signal lines, CPU data signal lines and CPU control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol; selecting a first subset of said protocol independent superset of processor-direct signal lines necessary for implementation of said first expansion bus protocol; and connecting said first subset of said protocol independent superset of processor-direct signal lines necessary for implementation of said first expansion bus protocol to a bus translator thereby forming a first expansion bus which functions in accordance with said first expansion bus protocol.
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Specification