Method of forming conductive interconnect structure

• US 5,441,914 A
• Filed: 05/02/1994
• Issued: 08/15/1995
• Est. Priority Date: 05/02/1994
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Gunderson, Craig D., Taft, Robert C., Sitaram, Arkalgud R.
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US08/236,076
• Time in Patent Office: 470 Days
• Field of Search: 437/228, 437/229, 437/192, 437/193, 437/200, 437/241, 437/189, 156/656, 156/653, 156/659.1, 156/660, 148/DIG. 12, 148/DIG. 1
• US Class Current: 438/592
• CPC Class Codes: H01L 21/0276 using an anti-reflective coating anti-reflective coating for lithography in general G03F7/09
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 23/53271 containing semiconductor material, e.g. polysilicon
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/012 Bonding, e.g. electrostatic for strain gauges

Abstract

In one embodiment, delamination of a patterned silicon nitride anti-reflective layer (26) from an underlying patterned tungsten silicide layer (32), is prevented by forming a thin silicon layer (30) between the patterned tungsten silicide layer (32) and the overlying patterned silicon nitride anti-reflective layer (26).

Claims

1. A method for forming a conductive interconnect in an integrated circuit comprising the steps of:

providing a semiconductor substrate;

forming a dielectric layer overlying the semiconductor substrate;

forming a conductive metal layer overlying the dielectric layer;

forming a silicon adhesion layer overlying the conductive metal layer;

forming an inorganic anti-reflective layer overlying the silicon adhesion layer;

etching the inorganic anti-reflective layer to form a remaining portion of the inorganic anti-reflective layer; and

etching the conductive metal layer to form the conductive interconnect, wherein the remaining portion of the inorganic anti-reflective layer overlies the conductive interconnect.

2. The method of claim 1, wherein the step of forming the inorganic anti-reflective layer is further characterized as forming a layer comprising silicon and nitrogen.

3. The method of claim 1, wherein the step of forming the silicon adhesion layer is further characterized as forming an amorphous silicon layer.

4. The method of claim 1, wherein the step of forming the silicon adhesion layer is further characterized as forming a polysilicon layer.

5. The method of claim 1, wherein the step of forming the conductive metal layer is further characterized as forming a metal silicide layer.

6. The method of claim 1, wherein the step of forming the conductive metal layer is further characterized as forming a conductive layer of material comprising a metal selected from the group consisting of tungsten, molybdenum, titanium, and cobalt.

7. The method of claim 1, wherein the step of forming the inorganic anti-reflective layer is further characterized as forming a silicon rich silicon nitride layer.

8. A method for forming a conductive interconnect in an integrated circuit comprising the steps of:

providing a semiconductor substrate;

forming a dielectric layer overlying the semiconductor substrate;

forming a metal layer overlying the dielectric layer;

forming a silicon adhesion layer overlying the metal layer;

forming a layer comprising silicon and nitrogen overlying the silicon adhesion layer;

etching the layer comprising silicon and nitrogen to form a remaining portion of the layer comprising silicon and nitrogen; and

etching the metal layer to form the conductive interconnect, wherein the remaining portion of the layer comprising silicon and nitrogen overlies the conductive interconnect.

9. The method of claim 8, further comprising the step of forming a doped silicon layer overlying the dielectric layer and underlying the metal layer.

10. The method of claim 9, wherein the step of forming the doped silicon layer is further characterized as forming a doped polysilicon layer.

11. The method of claim 9, wherein the step of forming the doped silicon layer comprises depositing a layer of amorphous silicon.

12. The method of claim 8, wherein the step of forming the metal layer is further characterized as forming a silicide layer comprising a metal selected from a group consisting of tungsten, titanium, molybdenum, and cobalt.

13. The method of claim 8, wherein the step of forming the silicon adhesion layer is further characterized as forming a polysilicon layer.

14. The method of claim 8, wherein the step of forming the silicon adhesion layer is further characterized as forming an amorphous silicon layer.

15. The method of claim 8, wherein the step of forming the dielectric layer is further characterized as forming a gate dielectric layer.

16. The method of claim 8, wherein the step of forming the layer comprising silicon and nitrogen is further characterized as forming a silicon rich silicon nitride anti-reflective layer.

17. A method for forming a conductive interconnect in an integrated circuit comprising the steps of:

providing a semiconductor substrate;

forming a dielectric layer overlying the semiconductor substrate;

forming a polysilicon layer overlying the dielectric layer;

forming a tungsten silicide layer overlying the polysilicon layer;

forming an amorphous silicon adhesion layer overlying the tungsten silicide layer;

forming an anti-reflective layer comprising silicon and nitrogen overlying the amorphous silicon adhesion layer;

etching the anti-reflective layer to form a remaining portion of the anti-reflective layer; and

etching the polysilicon layer to form the conductive interconnect, wherein the remaining portion of the anti-reflective layer overlies the conductive interconnect.

18. The method of claim 17, further comprising the step of annealing the tungsten silicide layer prior to forming the anti-reflective layer.

19. The method of claim 17, wherein the step of forming the anti-reflective layer is further characterized as forming a layer of silicon oxynitride.

20. The method of claim 17, wherein the step of forming the anti-reflective layer is further characterized as forming a layer of silicon nitride.

21. The method of claim 17, wherein the step of forming the anti-reflective layer is further characterized as forming a layer of silicon-rich silicon nitride.

22. The method of claim 17, further comprising the step of depositing an oxide layer overlying the anti-reflective layer.