Semiconductor device

• US 5,442,210 A
• Filed: 10/28/1993
• Issued: 08/15/1995
• Est. Priority Date: 11/12/1992
• Status: Expired due to Fees

• Current Assignee: Nippon Precision Circuits, Inc. (Seiko Group)
• Original Assignee: Nippon Precision Circuits, Inc. (Seiko Group)
• Inventors: Kanehachi, Kaoru
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US08/144,935
• Time in Patent Office: 656 Days
• Field of Search: 257/296, 257/298, 257/306, 257/314, 257/315, 257/316, 257/321
• US Class Current: 257/296
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region

Abstract

A semiconductor device has a DRAM portion forming a cache memory and a flash memory portion fabricated on a common substrate, fabricated by a process based on the process of fabricating the flash memory portion. An electrode layer common to capacitors of the DRAM portion and a floating gate layer of the flash memory portion are formed simultaneously from the same material. An electrode layer of the upper capacitor of the DRAM portion, a gate electrode layer for a transistor of the DRAM portion, and a control gate layer of the flash memory portion are formed simultaneously from the same material.

Claims

1. A semiconductor device comprising:

a DRAM portion;

a flash memory portion;

said DRAM portion and said flash memory portion both being formed on a main surface of a common semiconductor substrate;

a first insulation layer;

said DRAM portion having a first capacitor with a first electrode separated from said main surface of said substrate by said first insulation layer;

said flash memory portion having a floating gate separated from said main surface by said first insulation layer and formed of the same material as said first electrode; and

said first insulation layer in said flash memory portion forming a tunnel oxide film.

2. A semiconductor device according to claim 1 wherein said DRAM portion has a second capacitor with a second electrode separated from said first electrode by a second insulating layer, and a transistor with a gate electrode, and said flash memory portion has a control gate separated from said floating gate by said second insulating layer, said second electrode, gate electrode and control gate being formed of the same material.

3. A semiconductor device according to claim 2 wherein said substrate has a first heavily doped layer in said main surface connected to said second electrode via a hole in at least a part of said second insulating layer.

4. A semiconductor device according to claim 3 wherein said substrate has a second heavily doped layer in said main surface connected to said first electrode via a hole in said first insulating layer.

5. A semiconductor device comprising:

a DRAM portion having a first transistor and a flash memory portion having a second transistor;

said DRAM portion and said flash memory portion being formed on a main surface of a common substrate;

said first transistor and said second transistor being separate such that a drain of said first transistor and a drain of said second transistor are separated apart;

said DRAM portion having a first capacitor with a first electrode separated from said main surface of said substrate by a first insulation layer of said first capacitor;

said second transistor having a floating gate separated from said main surface of said substrate by a first insulation layer of said second transistor; and

said first insulation layer of said first capacitor and said first insulation layer of said second transistor being formed of the same material.

6. A semiconductor device comprising:

a DRAM portion having a first transistor and a flash memory portion having a second transistor;

said DRAM portion and said flash memory portion being formed on a main surface of a common substrate;

said first transistor and said second transistor being separate such that a drain of said first transistor and a drain of said second transistor are separated apart;

said DRAM portion having a first capacitor with a first electrode separated from said main surface of said substrate by a first insulation layer of said first capacitor;

said DRAM portion having a second capacitor with a second electrode separated from said first electrode by a second insulation layer of said first capacitor;

said second transistor having a floating gate separated from said main surface of said substrate by a first installation layer of said second transistor;

said second transistor having a control gate separated from said floating gate by a second insulation layer of said second transistor; and

said second insulation layer of said first capacitor and said second insulation layer of said second transistor being formed of the same material.

7. A semiconductor device comprising:

a DRAM portion having a first transistor and a flash memory portion having a second transistor;

said DRAM portion and said flash memory portion being formed on a main surface of a common substrate;

said first transistor and said second transistor being separate such that a drain of said first transistor and a drain of said second transistor are separated apart;

said DRAM portion having a first capacitor with a first electrode separated from said main surface of said substrate by a first insulation layer of said first capacitor;

said DRAM portion having a second capacitor with a second electrode separated from said first electrode by a second insulation layer of said first capacitor;

said second transistor having a floating gate separated from said main surface of said substrate by a first insulation layer of said second transistor;

said second transistor having a control gate separated from said floating gate by a second insulation layer of said second transistor; and

said second electrode and said control gate being formed of the same material.