VDMOS transistor and manufacturing method therefor

• US 5,442,214 A
• Filed: 10/28/1994
• Issued: 08/15/1995
• Est. Priority Date: 08/09/1994
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Yang, Sheng-Hsing
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/330,567
• Time in Patent Office: 291 Days
• Field of Search: 257/328, 257/332, 257/333, 257/335, 257/336, 257/345
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 148/126 Power FETs

Abstract

A VDMOS transistor having a reduced drain/source resistance without a corresponding decrease in breakdown voltage and a manufacturing method therefor. Such a VDMOS transistor is created by gradually increasing the doping density of the transistor'"'"'s implanted regions, while simultaneously increasing the respective thicknesses of the gate oxide layers corresponding to the implanted regions along the current flow path.

Claims

1. A VDMOS transistor on a semiconductor substrate, comprising:

a drain electrode region of a first conductivity type in said substrate, said drain electrode region having a drain electrode region doping density (D+);

an epitaxial layer of said first conductivity type formed on said drain electrode region, said epitaxial layer having an epitaxial layer doping density (D-), said epitaxial layer defining a first trench and a deeper and narrower second trench within said first trench, said epitaxial layer including a first implanted region of said first conductivity type adjoining said first trench and a second implanted region of said first conductivity type adjoining said second trench, said first and said second implanted regions having a first and a second implanted region doping density (D₁), (D₂), respectively;

a first gate oxide layer formed within said first trench adjacent to said first implanted region, said first gate oxide layer having a first gate oxide layer thickness (T_OX,D1); and

a second gate oxide layer formed within said second trench adjacent to said second implanted region, said second gate oxide layer having a second gate oxide layer thickness (T_OX,D2), wherein;

space="preserve" listing-type="equation">D-<

D.sub.1 <

D.sub.2 <

D+;

and

space="preserve" listing-type="equation">T.sub.OX,D1 <

T.sub.OX,D2.

2. The VDMOS transistor of claim 1, wherein said first conductivity type is N type.

3. The VDMOS transistor of claim 1, wherein said first conductivity type is P type.

4. The VDMOS transistor of claim 1, wherein said drain electrode region has a coefficient of drain electrode region electrical resistance between 0.005 and 0.1 Ω

-cm.

5. The VDMOS transistor of claim 1, wherein said epitaxial layer has a coefficient of epitaxial layer electrical resistance between 0.1 and 100 Ω

-cm and an epitaxial layer thickness between 8 and 100 μ

m.