Testing and exercising individual, unsingulated dies on a wafer

• US 5,442,282 A
• Filed: 07/02/1992
• Issued: 08/15/1995
• Est. Priority Date: 07/02/1992
• Status: Expired due to Term

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Dangelo, Carlos, Rostoker, Michael D., Koford, James
• Primary Examiner(s): NGUYEN, VINH P
• Application Number:
  US07/908,687
• Time in Patent Office: 1,139 Days
• Field of Search: 324/158 R, 324/73.1, 324/158 F, 324/158 P, 437/8, 257/48, 340/825.07
• US Class Current: 324/756.04
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]

Abstract

Signals (including probes) from an external system are selectively connected to a plurality of unsingulated dies on a semiconductor wafer with a minimum number of connections and an electronic selection mechanism resident on the wafer. The electronic selection mechanism is connected to the individual dies by conductive lines on the wafer. The electronic selection mechanism is capable of providing the external signals (or connecting the external probe) to a single die or groups of the dies, and electronically "walking through" the entire plurality of unsingulated dies. Redundant conductive lines may be provided. Diodes and/or fuses may be provided in conjunction with the conductive lines, to protect against various faults which may occur in the conductive lines. Redundant electronic selection mechanisms may also be provided to ensure the ability to selectively provide signals to the unsingulated dies.

Claims

1. A method of providing signals from a common external source to individual, unsingulated dies on a semiconductor wafer, comprising:

forming a plurality of individual integrated circuit dies on a semiconductor wafer, each die occupying a distinct one of a like plurality of first areas on the wafer;

providing an electronic selection mechanism in a second area of the wafer distinct from the plurality of first areas of the wafer;

providing pads for receiving signals from a source external to the wafer;

providing on each die, within the area of the die, an address decoding circuit associated with the die, each address decoding circuit being responsive to a unique address at a multibit address input of the address decoding circuit to permit the signals to be received by the die with which the address decoding circuit is associated;

causing the electronic selection mechanism to address one or more of the plurality dies, by Outputting a multi-bit address signal associated with the one or more dies;

providing a multi-bit address bus of conductive lines between the electronic selection mechanism and the plurality of dies;

receiving the signals from the external source; and

routing the signals, over the multi-bit address bus, to the selected one of more of the plurality of dies.

2. A method of providing signals from a common external source to individual, unsingulated dies on a semiconductor wafer, according to claim 1, further comprising:

connecting the external source to said pads with probes.

3. A method of providing signals from a common external source to individual, unsingulated dies on a semiconductor wafer, according to claim 1, further comprising:

connecting the external source to said pads with bond wires.