Single input single output rate optimal controller

• US 5,442,544 A
• Filed: 11/04/1994
• Issued: 08/15/1995
• Est. Priority Date: 01/26/1990
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Jelinek, Jan
• Primary Examiner(s): Envall, Jr., Roy N.
• Assistant Examiner(s): Brown, Thomas E.
• Application Number:
  US08/334,895
• Time in Patent Office: 284 Days
• Field of Search: 364/148-151, 364/160-163, 364/138, 364/166, 364/164-165, 364/152-153, 364/180
• US Class Current: 700/29
• CPC Class Codes: G05B 13/048 using a predictor

Abstract

A nonlinear, time-variable digital controller and a general method for its synthesis. The processing of the reference load and the disturbance changes are kept totally separated. This benefits the designer because he can treat any control task as a pure tracking problem in which one unit is responsible for planning and synthesizing the controlled system'"'"'s trajectory to move it into a desired state, and another unit takes care of possible deviations from the trajectory due to disturbance or load changes. Since the two units are independent, the designer is free to choose their characteristics arbitrarily.

Claims

1. A controller unit for controlling a plant comprising,

a reference processor having a reference input means for receiving a reference signal and being operable to generate a baseline control signal which can bring said plant into a desired state along a definite user defined path,

a reference model having a reference model identifying the system through the use of a transfer function for generating and outputting a signal representing the expected output of said plant at any instant along said user defined path,

a disturbance processor having an input for receiving error signals and being operable to generate and send corrective control signals,

each of said processors having an operating mode which is pursuant to either a fixed duration control law or a fixed rate control law, and

supervisor means for controlling maximum acceptable rate limits, connected to receive signals from and send signals to each of said reference processor, reference model, and disturbance processor so that said limits are not exceeded;

and wherein said reference model further comprises;

a feedforward path model of the plant under control, receiving as input a user defined set point, and generating and outputting a signal representing the expected output of said plant at that particular time instant, and

a feedback loop model, receiving an input from a disturbance model and generating and outputting a signal representing the expected effect U_D will have on the plant, and

a means for outputting the result of the combination of the output of the feedforward model and the feedback loop model to the disturbance processor.

2. A controller unit for controlling a plant as in claim 1, wherein the result of the combination of the output of the feedforward model and the feedback loop model are further combined with plant output signals before being provided to the disturbance processor.

3. A computer system operable as a predictive controller for controlling a plant and connected to said plant either through direct electronic or optical link or via human machine interface comprising:

a reference processor having a reference input for receiving a reference signal, indicative of setpoint, and being responsive to the user controllable setpoint, which reference processor generates a sequence of baseline control signals which can bring said plant into a desired state, as indicated by an output signal from said plant, along a user defined path,

a feedforward path model having an input which also receives said reference signal, being responsive to the user controllable set point to generate and output a sequence of signals representing the expected output of said plant at any instant along said user defined path,

a disturbance processor having an input for receiving a sequence of error signals which represent the difference between the actual and the predicted plant output and for generating and outputting a sequence of corrective control signals based on a control law,

an active robustness processor having an input also for receiving a sequence of error signals which represent the difference between the actual and the predicted plant output, and for generating and outputting a sequence of corrective control signals based on the input of said received sequence of error signals and its control law,

a disturbance feedback loop model having an input for receiving the sequence of error signals received by said disturbance processor and being operable to generate and output a sequence of signals representing disturbances that the disturbance processor has already processed,

an active robustness feedback loop model having an input for receiving the sequence of error signals received by said active robustness processor and being operable to generate and output a sequence of signals representing disturbances that the active robustness processor has already processed,

a disturbance feedback loop model summation unit having an input to receive the output sequence from the active robustness feedback loop model and the disturbance feedback loop model and an output means for producing an output sequence consisting of the element wise summation of the two input sequences,

a reference model summation unit having an input to receive the output sequence from the disturbance feedback loop model summation unit and the feedforward path model and an output means for producing an output sequence consisting of the element wise summation of the two input sequences,

a disturbance processor difference unit having an input to receive a sequence of signals from the reference model summation unit and an input to receive the output from the plant, and an output means to produce an output sequence consisting of the difference between the first term of the sequence and the plant output,

a disturbance switching decision unit having;

an input for receiving the output from the disturbance processor summation unit, a comparison means for comparing the level of the disturbance to a user defined level, and a switching means that outputs the received signal to either the disturbance processor or the active robustness processor, based on the signal comparison,

a reference processor summation unit having inputs to receive the output sequence from the reference processor and of the disturbance processor and an output for producing a sequence consisting of the element wise summation of the two input sequences,

an active robustness summation unit having an inputs to receive the output sequence from the reference processor summation unit and of the active robustness disturbance processor and an output for producing an output sequence consisting of the element wise summation of the two input sequences,

wherein said feedback loop model, active robustness feedback loop model, disturbance processor and active robustness processor obtain their inputs from the disturbance processor summation unit.

4. A computer system operable as a predictive controller as set forth in claim 3 which further comprises:

a limit checking supervisor having an input to receive the output sequence from the active robustness summation unit processor and an output for producing an output sequence in which none of the elements in said sequence violate user defined limits.

5. A computer system operable as a predictive controller as set forth in claim 3 which further comprises:

a limit checking supervisor having an input to receive the output sequence from the active robustness summation unit processor and an output for producing an output sequence in which none of the combination of elements in said sequence violate user defined limits.

6. A computer system operable as a predictive controller as set forth in claim 3 wherein the reference processor summation unit and the active robustness summation unit include:

a limit checking supervisor that regulates the output sequence to ensure that none of the elements in said sequence violate user defined limits.

7. A computer system operable as a predictive controller as set forth in claim 3 wherein the reference processor summation unit and the active robustness summation unit include:

a limit checking supervisor that regulates the output sequence to ensure that none of the combination of elements in said sequence violate user defined limits.

8. A computer system operable as a predictive controller for controlling a plant and connected to said plant either through direct electronic or optical link or via human machine interface comprising:

a reference processor having a reference input for receiving a reference signal, indicative of setpoint, and being responsive to the user controlled set point to generate a sequence of baseline control signals which can bring said plant into a desired state as indicated by its output signal, along a user defined path,

a feedforward path model having an input which also receives said reference signal, being responsive to the user controlled set point to generate and output a sequence of signals representing the expected output of said plant at any instant along said user defined path,

a disturbance processor having an input for receiving a sequence of error signals which represent the difference between the actual and the predicted plant output and for generating and outputting a sequence of corrective control signals based on a control law,

a feedback loop model having an input for receiving a sequence of error signals representing the difference between the actual and predicted plant output and being operable to generate and output a sequence of signals representing disturbances that the disturbance processor has already processed,

a reference model summation unit having an input to receive the output sequence from the feedback loop model and the feedforward path model and an output means for producing an output sequence consisting of the element wise summation of the two input sequences,

a disturbance processor summation unit having an input to receive a sequence of signals from the reference model summation unit and an input to receive the output from the plant, and an output means to produce an output sequence consisting of the difference between the sequence and the plant output,

a reference processor summation unit having an input to receive the output sequence from the reference processor and the disturbance processor and an output for producing an output sequence consisting of the element wise summation of the two input sequences,

wherein said feedback loop model and disturbance processor obtain their inputs from the disturbance processor summation unit.

9. A controller unit according to claim 8 wherein said reference processor summation unit reduces each term of the output sequence by the same proportion when one of the elements exceeds a user defined limit.

10. A controller unit according to claim 8 wherein said reference processor summation unit reduces each term of the output sequence by the same proportion when the change between one element and another exceeds a user defined limit.

11. A controller unit according to claim 8 wherein said reference processor summation unit reduces each term of the disturbance processor output sequence by the same proportion when one or more of the elements when added with the reference processor sequence would exceed a user defined limit.

12. A controller unit according to claim 8 wherein said reference processor summation unit reduces each term of the disturbance processor output sequence by the same proportion when the change between any element and another when added with the reference processor sequence would exceed a user defined limit.

13. A controller unit according to claim 8 wherein said reference processor summation unit reduces each term of the reference processor output sequence by the same proportion when one or more of the elements when added with the disturbance processor sequence would exceed a user defined limit.

14. A controller unit according to claim 8 wherein said reference processor summation unit reduces each term of the reference processor output sequence by the same proportion when the change between any element and another when added with the disturbance processor sequence would exceed a user defined limit.

15. A method for controlling a plant using a controller unit for controlling a plant wherein said controller unit has:

a reference processor having a reference input means for receiving a reference signal and being operable to generate a baseline control signal which can bring said plant into a desired state along a definite user defined path,

a reference model for generating and outputting a signal representing the expected output of said plant at any instant along said path,

a disturbance processor having an input for receiving error signals and being operable to generate and output corrective control signals according to a user defined control law,

each of said processors having an operating mode which is user defined, and wherein said method for controlling said plant employs a method for coordinating the operation of said processors, comprising the steps of;

(A) first;

(i) defining a reference model which identifies the plant, and

(ii) selecting a user defined control law for the reference processor and the disturbance processor or a global law for both,

(B) then in any order;

(i) allowing the user to adjust the setpoint,

(ii) generating a baseline reference control signal (U_R) through a processor unit obeying said control law,

(iii) generating a disturbance corrective signal (U_D) through a processor unit based on the deviation between the output from the plant and the expected output as generated by the reference model, but not including disturbances which have already had a corrective signal generated for them,

(iv) then combining U_R and U_D to produce a control signal for said plant so that the control law(s) selected for the disturbance processor and the reference processor or the global control law for the plant are not violated.

16. A method as recited in claim 15, for controlling a plant which further comprises:

(A) reducing U_R to user defined maximum and minimum control values when said maximum or minimum control values are violated;

(B) reducing U_R to user defined maximum and minimum control rates of change when said maximum or minimum control rates of change are violated.

17. A method as recited in claim 15, for controlling a plant which further comprises:

(A) reducing U_D to user defined maximum and minimum control values when said maximum or minimum control values are violated;

(B) reducing U_D to user defined maximum and minimum control rates of change when said maximum or minimum control rates of change are violated.

18. A method for controlling a plant using a controller as recited in claim 15 which further comprises the steps of:

(A) reducing the combination of U_R and U_D to the user defined maximum and minimum output values when said maximum or minimum values are violated;

(B) reducing the combination of U_R and U_D to the user defined maximum and minimum output rates of change, when said minimum or maximum rates are violated.