Flexible multiport multiformat burst buffer

• US 5,442,747 A
• Filed: 09/27/1993
• Issued: 08/15/1995
• Est. Priority Date: 09/27/1993
• Status: Expired due to Term

• Current Assignee: Creative Technology Ltd.
• Original Assignee: Auravision Corporation
• Inventors: Simpson, Miles S., Chan, Steven S., Kimura, Scott A.
• Primary Examiner(s): Powell, Mark R.
• Assistant Examiner(s): Tung, Kee M.
• Application Number:
  US08/127,219
• Time in Patent Office: 687 Days
• Field of Search: 395/164-166, 395/154, 395/400, 395/425, 395/250, 395/275, 365/189.01, 365/189.04, 365/189.05, 365/189.12, 365/230.02, 365/230.05, 365/230.08, 365/230.09
• US Class Current: 345/543
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches

Abstract

A multimedia video processor chip for a personal computer in employs a multi-port central cache memory to queue all the incoming data to be stored in a DRAM and all the outgoing data being retrieved from the DRAM. Such a cache memory is used in one of several modes in which the cache memory is partitioned by cache boundaries into different groups of storage areas. Each storage area of the cache is dedicated to storing data from a specific data source. The cache boundaries are chosen such that, for a given mode, the storage areas are optimized for worst case conditions for all data streams.

Claims

1. A video image memory system comprising:

a buffer memory having at least one input data port for accepting incoming data to be stored in said buffer memory, at least one write address port for receiving addresses designating locations where said incoming data is to be stored in said buffer memory, at least one output data port for outputting data retrieved from said buffer memory, and at least one read address port for receiving addresses designating locations of stored data in said buffer memory to be outputted,

each of said locations corresponding to one of a plurality of storage registers in said buffer memory;

a plurality of data sources connected to said at least one input data port for generating data to be buffered by said buffer memory;

a read addressing means for each of said data sources, each of said read addressing means being connected to said at least one read address port for generating an address for retrieving data associated with each of said data sources from said buffer memory;

a write addressing means for each of said data sources, each of said write addressing means being connected to said at least one write address port for generating an address for storing data associated with each of said data sources into said buffer memory; and

a boundary control circuit connected to said buffer memory for allocating a different group of said registers in said buffer memory to buffer data from different ones of said data sources such that each group of registers only contains data from a single one of said data sources, said boundary control circuit selecting a size of each group of registers depending upon a particular mode of operation selected for said video image memory system, said mode being selected based on requirements of said buffer memory to buffer said data from said data sources,

said boundary control circuit being connected to control each of said read addressing means and each of said write addressing means to selectively address only those registers in a designated group of registers, each group of registers being designated to store data from only a single data source.

2. The system of claim 1 further comprising

a first multiplexer means having two or more data receiving ports, each data receiving port for receiving data from a different one of said plurality of data sources, said first multiplexer means having a control terminal connected to receive a signal designating which one of said data receiving ports to connect to a first multiplexer output port, said first multiplexer output port being connected to one of said at least one input data port of said buffer memory.

3. The system of claim 2 further comprising a second multiplexer means having two or more address receiving ports, each address receiving port for receiving an address from a different one of said write addressing means, said second multiplexer means having a control terminal connected to receive a signal designating which of said address receiving ports to connect to a second multiplexer output port, said second multiplexer output port being connected to one of said at least one write address port of said buffer memory.

4. The system of claim 1 further comprising a dynamic random access memory (DRAM) having an input connected to receive data outputted from said at least one output data port of said buffer memory.

5. The system of claim 1 wherein said boundary control circuit controls said read addressing means and said write addressing means to only generate addresses within said designated group of registers, said read addressing means and said write addressing means being incremented upon application of a clock signal to said read addressing means and said write addressing means.

6. The system of claim 1 wherein said boundary control circuit comprises one or more cache boundary registers which are loaded with preset values associated with said particular mode of operation being selected, said preset values providing control signals for controlling said boundary control circuit to allocate a different group of said registers in said buffer memory to buffer data from different ones of said data sources.

7. A method of operating a system for buffering data to be stored in and retrieve from a video memory, said method comprising the steps of:

selecting one or more data streams from a set of

data streams to be buffered by a buffer memory;

and

allocating a different group of registers in said buffer memory to buffer data from different ones of said data streams which have been selected, such that each group of registers only contains data from a single one of said data streams, a size of each group of registers depending upon a particular mode of operation selected for said system, said mode being selected based on requirements of said buffer memory to buffer data from said data streams selected.

8. The method of claim 7 wherein said step of allocating comprises the step of controlling read addressing means associated with each of said data streams selected and write addressing means associated with each of said data streams selected to selectively address only those registers in a designated group of said registers in said buffer memory, each group of registers being designated to store data from only a single one of said data streams.