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Dynamic random access memory with bit line equalizing means

  • US 5,444,662 A
  • Filed: 06/08/1994
  • Issued: 08/22/1995
  • Est. Priority Date: 12/04/1991
  • Status: Expired due to Term
First Claim
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1. A dynamic random access memory with bit line equalizing circuit, comprising:

  • a plurality of pairs of dynamic memory cells, including a first memory cell pair having first and second dynamic memory cells;

    a plurality of word lines, including a first word line pair having first and second word lines for respectively selecting the first memory cell and the second memory cell;

    a plurality of pairs of bit lines, including a first bit line pair having first and second complementary bit lines which cross said first and second word lines, said first memory cell being connected to cross-over portions of said first bit line and said first word line;

    a sense amplifier circuit having first and second nodes;

    a plurality of pairs of transfer gates, including a first transfer gate pair having first and second transfer gates for respectively connecting the first bit line to the first node and the second bit line to the second node;

    a node equalizing circuit means for setting the potentials on the first and second nodes equal to each other, the node equalizing circuit means including first, second, and third transistors, each of the first, second, and third transistors having first, second, and gate electrodes, the first electrodes of the first and second transistors being connected to a potential of one-half of a source voltage level, the second electrode of the first transistor being connected to the first electrode of the third transistor, the second electrode of the second transistor being connected to the second electrode of the third transistor, the first electrode of the third transistor being connected to the first node, the second electrode of the third transistor being connected to the second node, and the gate electrodes of the first, second, and third transistors receiving a first equalizing signal; and

    said bit line equalizing circuit comprising bit line equalizing circuit means for setting the potentials on the first and second bit lines equal to each other, the bit line equalizing circuit means including fourth, fifth, and sixth transistors, each of the fourth, fifth, and sixth transistors having first, second, and gate electrodes, the first electrodes of the fourth and fifth transistors being connected to potential of one-half of the source voltage level, the second electrode of the fourth transistor being connected to the first electrode of the sixth transistor, the second electrode of the fifth transistor being connected to the second electrode of the sixth transistor, the first electrode of the sixth transistor being connected to the first bit line, the second electrode of the sixth transistor being connected to the second bit line, and the gate electrodes of the fourth, fifth, and sixth transistors receiving a second equalizing signal.

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