Dynamic random access memory with bit line equalizing means

• US 5,444,662 A
• Filed: 06/08/1994
• Issued: 08/22/1995
• Est. Priority Date: 12/04/1991
• Status: Expired due to Term

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Murashima, Yoshihiro, Ueno, Joji, Tanaka, Takayuki, Tokunaga, Yasuhiro, Yonaga, Takeru, Sekino, Yoshimasa
• Primary Examiner(s): Popek, Joseph A.
• Assistant Examiner(s): Nguyen, Tan
• Application Number:
  US08/257,450
• Time in Patent Office: 440 Days
• Field of Search: 365/203, 365/149, 365/205, 365/190, 365/207, 365/208, 365/202
• US Class Current: 365/203
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits

Abstract

A dynamic random access memory of the complementary MOS transistor type has memory cells connected between complementary bit lines on one side of a pair of transfer gates and a sense amplifier connected to nodes on the other side of the transfer gates, so that the sense amplifier can be connected to the bit lines and memory cells through the pair of transfer gates. A sense amplifier equalizing circuit and a bit line equalizing circuit are provided on opposite sides of the transfer gates so that the potentials on the bit lines can be equalized independently of equalization of the potentials on the nodes. Accordingly, there is no delay in the equalization due to the transfer gates connecting the nodes to the bit lines. According to another aspect of the invention, the transfer gates each include a pair of MOSFET transistors connected to each other in parallel, wherein one transistor of each pair of MOSFET transistors is an n-channel MOSFET transistor and the other transistor of each pair of MOSFET transistors is a p-channel MOSFET transistor. By, for example, connecting the gate of the NMOS transistor of each transfer to the power source and connecting the gate of each PMOS transistor to the ground, it is possible to prevent erroneous operation of the DRAM from a drop in the gate potential.

Claims

1. A dynamic random access memory with bit line equalizing circuit, comprising:

a plurality of pairs of dynamic memory cells, including a first memory cell pair having first and second dynamic memory cells;

a plurality of word lines, including a first word line pair having first and second word lines for respectively selecting the first memory cell and the second memory cell;

a plurality of pairs of bit lines, including a first bit line pair having first and second complementary bit lines which cross said first and second word lines, said first memory cell being connected to cross-over portions of said first bit line and said first word line;

a sense amplifier circuit having first and second nodes;

a plurality of pairs of transfer gates, including a first transfer gate pair having first and second transfer gates for respectively connecting the first bit line to the first node and the second bit line to the second node;

a node equalizing circuit means for setting the potentials on the first and second nodes equal to each other, the node equalizing circuit means including first, second, and third transistors, each of the first, second, and third transistors having first, second, and gate electrodes, the first electrodes of the first and second transistors being connected to a potential of one-half of a source voltage level, the second electrode of the first transistor being connected to the first electrode of the third transistor, the second electrode of the second transistor being connected to the second electrode of the third transistor, the first electrode of the third transistor being connected to the first node, the second electrode of the third transistor being connected to the second node, and the gate electrodes of the first, second, and third transistors receiving a first equalizing signal; and

said bit line equalizing circuit comprising bit line equalizing circuit means for setting the potentials on the first and second bit lines equal to each other, the bit line equalizing circuit means including fourth, fifth, and sixth transistors, each of the fourth, fifth, and sixth transistors having first, second, and gate electrodes, the first electrodes of the fourth and fifth transistors being connected to potential of one-half of the source voltage level, the second electrode of the fourth transistor being connected to the first electrode of the sixth transistor, the second electrode of the fifth transistor being connected to the second electrode of the sixth transistor, the first electrode of the sixth transistor being connected to the first bit line, the second electrode of the sixth transistor being connected to the second bit line, and the gate electrodes of the fourth, fifth, and sixth transistors receiving a second equalizing signal.

2. A dynamic random access memory according to claim 1, wherein said sense amplifier circuit includes a first sense amplifier which comprises n-channel MOSFET transistors and a second sense amplifier which comprises p-channel MOSFET transistors, said first sense amplifier sensing and amplifying a difference between a first potential on said first node and a second potential on said second node, when the first potential exceeds the second potential, and said second sense amplifier sensing and amplifying a difference between the first potential and the second potential, when the second potential exceeds the first potential.

3. A dynamic random access memory according to claim 1, wherein:

said plurality of pairs of dynamic memory cells additionally include a second memory cell pair having third and fourth dynamic memory cells;

said plurality of pairs of word lines additionally include a second word line pair having third and fourth word lines for respectively selecting the third memory cell and the fourth memory cell;

said plurality of pairs of bit lines additionally include a second bit line pair having third and fourth complementary bit lines which cross said third and fourth word lines, said third memory cell being connected to cross-over portions of said third bit line and said third word line and said fourth memory cell being connected to cross-over portions of said fourth bit line and said fourth word line;

said plurality of pairs of transfer gates additionally include a second transfer gate pair having third and fourth transfer gates for respectively connecting said third bit line to said first node and said fourth bit line to said second node; and

said dynamic random access memory further comprises third equalizing circuit means, responsive to a third equalization signal, for setting the potentials on the third and fourth bit lines equal to each other.

4. A dynamic random access memory according to claim 1, wherein said first transfer gate comprises a first n-channel MOSFET transistor and a first p-channel MOSFET transistor, connected to each other in parallel, and wherein said second transfer gate comprises a second n-channel MOSFET transistor and a second p-channel MOSFET transistor, connected to each other in parallel.

5. A dynamic random access memory according to claim 4, wherein said sense amplifier circuit includes a first sense amplifier which comprises n-channel MOSFET transistors and a second sense amplifier which comprises p-channel MOSFET transistors, said first sense amplifier sensing and amplifying a difference between a first potential on said first node and a second potential on said second node, when the first potential exceeds the second potential, and said second sensor amplifier sensing and amplifying a difference between the first potential and the second potential, when the second potential exceeds the first potential.

6. A dynamic random access memory according to claim 4, wherein said MOSFET transistors of said first and second transfer gates have gate electrodes, and the gate electrodes of said n-channel MOSFET transistors of said first and second transfer gates receive a potential of the source voltage level and the gate electrodes of said p-channel MOSFET transistors of said first and second transfer gates receive a potential of a ground voltage level.

7. A dynamic random access memory according to claim 4, wherein:

said plurality of pairs of dynamic memory cells additionally include a second memory cell pair having third and fourth dynamic memory cells;

said plurality of pairs of word lines additionally include a second word line pair having third and fourth word lines for respectively selecting the third memory cell and the fourth memory cell;

said plurality of pairs of bit lines additionally include a second bit line pair having third and fourth complementary bit lines which cross said third and fourth word lines, said third memory cell being connected to cross-over portions of said third bit line and said third word line and said fourth memory cell being connected to cross-over portions of said fourth bit line and said fourth word line; and

said plurality of pairs of transfer gates additionally include a second transfer gate pair having third and fourth transfer gates for respectively connecting said third bit line to said first node and said fourth bit line to said second node, said third transfer gate including a third n-channel MOSFET transistor and a third p-channel MOSFET transistor, connected to each other in parallel, and said fourth transfer gate including a fourth n-channel MOSFET transistor and a fourth p-channel MOSFET transistor, connected to each other in parallel.

8. A dynamic random access memory according to claim 7, wherein said MOSFET transistors of said third and fourth transfer gates have gate electrodes, and the gate electrodes of said n-channel MOSFET transistors of said third and fourth transfer gates receive a potential of the source voltage level and the gate electrodes of said p-channel MOSFET transistors of said third and fourth transfer gates receive a potential of a ground voltage level.

9. A dynamic random access memory according to claim 7, further comprising:

third equalizing circuit means, responsive to a third equalization signal, for setting the potentials on the third and fourth bit lines equal to each other.

10. A dynamic random access memory according to claim 1, wherein said second memory cell is connected to cross-over portions of said second bit line and said second word line.