Adjustable error-correction composite Reed-Solomon encoder/syndrome generator

• US 5,444,719 A
• Filed: 01/26/1993
• Issued: 08/22/1995
• Est. Priority Date: 01/26/1993
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cox, Charles E., Schwiegelshohn, Uwe, Fettweis, Gerhard P., Hassner, Martin A.
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US08/008,922
• Time in Patent Office: 938 Days
• Field of Search: 371/37.1, 371/40.1, 371/41
• US Class Current: 714/769
• CPC Class Codes: G11B 20/1833 by adding special lists or symbols to the coded information G11B20/1806, G11B20/1866 take precedence
• CPC Class Codes: H03M 13/151 using error location or error correction polynomials
• CPC Class Codes: H03M 13/35 Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics

Abstract

A composite encoder/syndrome generating circuit computes both check symbols and error syndromes using a single set of multiplier devices with varying tap weights having values that provide a maximum preselected error correction capability but is readily adjustable, such as by programmable latches, to eliminate from the circuit selectable multiplier devices to reduce the error correction capability without requiring a change in the tap weight values. The circuit may be used to increase or decrease error correction capability (a) according to which of a plurality of concentric bands of recording tracks is being accessed in a banded direct access data storage device, (b) according to noise level as sensed in a data communications channel having an output subject to noise, or (c) according to changes in sending rates in a sending device that sends data at variable rates.

Claims

1. An algebraic error correction system, comprising:

a composite encoder/syndrome generating circuit for generating both check symbols and error syndromes, said circuit comprising a single set of multiplier devices that have tap weights with preselected values for computing the check symbols and also computing the error syndromes used to determine error locations and values, the complete set of multiplier devices providing a maximum preselected error correction capability; and

means for selectively adjusting the number of said multiplier devices from the set included in said circuit to provide a desired error correction capability less than said maximum capability without requiring changes in the values of the tap weights.

2. The system of claim 1, including:

a direct access storage device having at least one disk with data stored on recording tracks in concentric bands;

an actuator for accessing data on selectable tracks within selected ones of said bands; and

a sensor for sensing the location of the band being accessed, said sensor being interposed in a feedback circuit between the actuator and encoder/syndrome generating circuit and operative to condition said adjusting means to selectively adjust the error correction capability according to the particular band being accessed by the actuator.

3. The system of claim 1, including a data source, a communications channel with an output subject to noise, and a noise level sensor in a feedback circuit between the channel output and encoder/syndrome generating circuit for conditioning said adjusting means to increase or decrease the error correction capability according to whether the noise level as sensed by said sensor increases or decreases, respectively.

4. The system of claim 1, including a data network comprising a data receiver having an input, a data sender for sending data at variable sending rates via the encoder/syndrome generating circuit to the data receiver, and a sensor interposed in a feedback circuit between the input to the receiver and the encoder/syndrome generating circuit and responsive to changes in sending rates to condition said adjusting means to increase or decrease the error correction capability according to whether the sending rate increases or decreases, respectively.

5. A method of adjusting error correction capability in at least one system from a group of systems including a direct access storage system, data communications system, or data network system, including the steps of:

providing in a circuit a single set of multiplier devices with tap weights having values preselected for computing values for both check symbols and for error syndromes necessary to determine error locations and values for providing a maximum preselected error correction capability; and

selectively adjusting the number of said multiplier devices included in the circuit to provide a desired error correction capability less than said maximum capability without requiring changes in the values of the tap weights.

6. A data processing system comprising:

a controller;

a channel;

a buffer;

a decoder;

a circuit comprising means operative during an encoding operation to generate check symbols and during a decoding operation to generate error syndromes, said circuit comprising;

(i) multiplier devices that have tap weights with preselected values for computing the check symbols and also computing the error syndromes for providing a maximum preselected error correction capability when all of said multiplier devices are included in the circuit; and

(ii) means for selectively adjusting the number of said multiplier devices included in said circuit to provide a desired error correction capability less than said maximum capability without requiring changes in the values of the tap weights; and

means (39A, 39B, 39C, 42, 43,

     44) conditioned by said controller to select between encoding and decoding operations and, for either of these operations, between either of two operating conditions for said circuit, said circuit being operative while in one condition during an encoding operation to pass data to the channel and generate the check symbols and while in the other condition during the encoding operation to pass the check bytes to the channel, said circuit being operative while in said one condition during a decoding operation to pass data from the channel to the buffer and generate the error syndromes, and while in said other position during the decoding operation to pass the error syndromes to the decoder.

7. The system of claim 6, including programmable means (41) for adjusting the number of multiplier devices included in the circuit.

8. The system of claim 6, including means (41) for adaptively adjusting the number of multiplier devices included in the circuit.

9. The system of claim 6, wherein the circuit is used for encoding and decoding operations utilizing Reed-Solomon error correcting codes.