Semiconductor integrated circuit device carrying out parallel operational processing with electronically implemented neural network

• US 5,444,822 A
• Filed: 06/16/1993
• Issued: 08/22/1995
• Est. Priority Date: 07/28/1992
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Shinohara, Hirofumi
• Primary Examiner(s): MacDonald, Allen R.
• Assistant Examiner(s): Dorvil, Richemond
• Application Number:
  US08/077,143
• Time in Patent Office: 797 Days
• Field of Search: 395/27, 395/21, 395/24
• US Class Current: 706/41
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

A semiconductor integrated circuit device electrically simulating a vital neural network includes neuron units. Each neuron unit includes a plurality of laterally connected synapse units, an accumulator for accumulatively adding the outputs of the final synapse unit in the lateral connection, and a nonlinear processor for carrying out a predetermined nonlinear operational processing on the output of the accumulator. The number of the neuron units and the number of synapse units per neuron unit satisfy a relation of an integer multiple. The number of regularly operating neuron units can be made equal to that of the synapse units per neuron unit, whereby it is possible to prevent the neuron units from performing meaningless operations and an efficient neural network can be obtained.

Claims

1. A parallel operation semiconductor integrated circuit device comprising:

a plurality of first operational means for carrying out a predetermined operation of first data and predetermined second data;

a plurality of second operational means provided corresponding to said plurality of first operational means, each for receiving an output of a corresponding first operational means at a first input;

first connection means for cascade connecting said plurality of second operational means with each other, said first connection means comprising means for connecting said plurality of second operational means in a lateral connection in which an output of an upstream second operational means is connected to a second input of a second operational means subsequent to said upstream second operational means in the cascade connection; and

nonlinear conversion means for carrying out a nonlinear conversion processing on an output of a final second operational means in the cascade connection.

2. A parallel operational semiconductor integrated circuit device in accordance with claim 1, wherein each first operational means corresponding to respective second operational means receives different data as said first data.

3. A parallel operational semiconductor integrated circuit device in accordance with claim 1, wherein said nonlinear conversion means comprises:

accumulation means for accumulating an output of said final second operational means, and

nonlinear operational means for carrying out a predetermined nonlinear operational processing on the output of said accumulation means.

4. A parallel operational semiconductor integrated circuit device in accordance with claim 1, wherein each of said first operational means comprises digital multiplier for multiplying said first data by said second data.

5. A parallel operational semiconductor integrated circuit device in accordance with claim 1, wherein said first operational means comprises absolute differential value circuit for obtaining an absolute differential value of said first and second data.

6. A parallel operational semiconductor integrated circuit device in accordance with claim 1, wherein said second operational means comprises addition means for adding supplied data.

7. A parallel operational semiconductor integrated circuit device in accordance with claim 1, wherein each said second operational means comprises a plurality of full adders in parallel with each other, all outputs of said full adders are supplied to inputs of a subsequent second operational means.

8. A parallel operational semiconductor integrated circuit device in accordance with claim 7, wherein said nonlinear conversion means comprises:

final addition means for adding outputs of said final second operational means,

accumulation means for accumulating outputs of said final addition means, and

nonlinear operational processing means for carrying out a nonlinear operational processing on an output of said accumulation means.

9. A parallel operational semiconductor integrated circuit device in accordance with claim 1, wherein said first data comprises a plurality of bits, and said first operational means successively receive said first data in a bit by bit serial sequence and said nonlinear conversion means parallelly outputs data of a plurality of bits in a bit parallel mode, and wherein

said parallel operational semiconductor integrated circuit device further comprises:

shift means positioned between an output of said first operational means and an input of said nonlinear conversion means for shifting bits in position of supplied data, and

parallel-to-serial conversion means for converting a parallel output of said nonlinear conversion means to a bit serial output.

10. A parallel operational semiconductor integrated circuit device in accordance with claim 1, wherein said plurality of first and second operational means are divided into a plurality of groups said first connection means laterally connecting said plurality of second operational means in respective groups, and wherein

said parallel operational semiconductor integrated circuit device further comprises a third operational means for receiving outputs of the final second operational means in each of said groups, carrying out the same operational processing as said second operational means on received data and supplying a result of said operational processing to said nonlinear conversion means.

11. A parallel operational semiconductor integrated circuit device comprising:

a plurality of processing units each comprising (a) a plurality of first operational means for carrying out a predetermined operation of a first data and a predetermined second data, (b) a plurality of second operational means each corresponding to an output of a respective one of said plurality of first operational means for carrying out predetermined operational processing on supplied data, (c) first connection means for connecting said plurality of second operational means in a lateral connection in which an output of a second operational means is connected to a second input of a subsequent second operational means, and (d) nonlinear conversion means for carrying out a nonlinear conversion processing on an output of a final second operational means in the lateral connection; and

second connection means for supplying outputs of said nonlinear conversion means in the respective processing units to the respective processing units in common as said first data, the number of said second connection means depending on the number of said nonlinear conversion means of said processing units and the number of said first operational means comprised in a single processing unit.

12. A parallel operational semiconductor integrated circuit device in accordance with claim 11, wherein

numbers of said first and second operational means comprised in a single processing unit are identical to each other while the number of said processing units is N times the number of said second connection means, where said N represents a natural number, and wherein

said parallel operational semiconductor integrated circuit device further comprises multiplexing means for multiplexingly coupling outputs of said nonlinear conversion means comprised in said N processing units with a single first operational means in respective processing units.

13. A parallel operational system comprising:

a plurality of semiconductor integrated circuits each being formed on a semiconductor chip and each comprising (a) first operational means for carrying out a predetermined operation of a first data and a predetermined second data, (b) second operational means provided in correspondence to said first operational means each for receiving an output of a corresponding first operational means at a first input thereof, (c) first connection means for connecting said second operational means in a lateral connection in which outputs of respective second operational means are coupled to respective second inputs of subsequent second operational means, and (d) nonlinear conversion means for carrying out a nonlinear conversion processing on an output of the finally connected second operational means in said lateral connection; and

second connection means for supplying outputs of said nonlinear conversion processing means provided in respective semiconductor integrated circuits in common to respective semiconductor integrated circuits as said first data, the number of said second connection means depending on the number of outputs of said nonlinear conversion means in a single semiconductor integrated circuit and the number of said first operational means included in a single semiconductor integrated circuit.

14. A system in accordance with claim 13, wherein a single of said semiconductor integrated circuits comprises N said nonlinear conversion means and M said first operational means per said nonlinear conversion means, with K said semiconductor integrated circuits being provided in parallel, where N, K and M represent integers satisfying a relation of N.K=M, and wherein

said second connection means comprises means for transmitting all outputs of respective said nonlinear conversion means of respective said semiconductor integrated circuits to respective said first operational means in parallel.

15. A semiconductor integrated circuit device comprising:

a plurality of processing units each comprising (a) operational means for carrying out an operation of a first data and a predetermined second data, and (b) a memory comprising a plurality of memory cells for storing said second data; and

memory cell selection means having at least a part of selection function in common for said plurality of processing units for selecting memory cells from respective memories in accordance with an address signal.