Translator system for message transfers between digital units operating on different message protocols and different clock rates

• US 5,444,860 A
• Filed: 02/14/1992
• Issued: 08/22/1995
• Est. Priority Date: 02/14/1992
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Ricci, Paul B., Datwyler, Wayne C.
• Primary Examiner(s): Treat, William M.
• Application Number:
  US07/837,174
• Time in Patent Office: 1,285 Days
• Field of Search: 395/200, 395/250, 395/275, 395/325, 395/500, 395/800
• US Class Current: 710/52
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence

Abstract

A message transfer system between digital modules where two or more digital modules operate on separate and different message lengths and clock frequencies and where, temporary storage buffer (translator unit) holds messages being transferred between the different digital modules and acts as a speed matching and word length matching buffer unit to permit compatible transfer of message words. Also, the transfer system recognizes when requests are outstanding from both digital modules and can discard a message from a requesting module. Each of the two or more separate digital modules is serviced by dual system busses providing for redundancy of data transfer operations.

Claims

1. A message transfer system for accommodating message transfers between digital units operating on different message protocols comprising:

(a) processor means , operating at a first clock rate, for sending and receiving message data at a rate of one single 48-bit word message per message cycle;

(b) resource means, operating at a second clock rate, for sending and receiving message data at a rate of four 48-bit word messages per message cycle;

(c) translation means connecting said processor means and said resource means and including;

(c1) means for accumulating and converting said processor derived single word messages into four 48-bit word messages for delivery to said resource means;

(c2) means for accumulating said resource derived 48-bit word messages for delivery to said processor means at a rate of one single 48-bit word message per message cycle;

(c3) translator controller means for regulating the transfer of said word messages between said processor means and said means for accumulating processor derived single word messages, and for regulating the transfer of words between said resource means and said means for accumulating resource derived 48-bit word messages, and including;

(c3a) message status register means, for indicating to said processor means, that a request from said processor means is still incomplete;

(d) dual system bus means providing first and second busses connecting said translation means to said resource means wherein each one of said busses operates concurrently to facilitate data transfers and wherein any one of said busses alone can provide data transfer operations if the other bus is disabled.

2. The message transfer system of claim 1 wherein said translator means further includes:

(a) said translator controller means providing connections to a programmable array logic counter means, a translator static RAM memory means, and to said processor means and resource means, said controller means comprising;

(1) a first state machine (SENDS) for accepting said single 48-bit word messages sent by said processor means for storage in said translator static RAM memory means;

(2) a second state machine (READS) providing logic to enable said processor means to read compatible messages of said single 48-bit word messages;

(3) a third state machine (MSGIN) providing logic to permit said resource means to compatibly write said four 48-bit word messages into said translator static RAM memory means;

(b) said programmable array logic counter means for addressing and accessing said single 48-bit and said four 48-bit word messages from said translator static RAM memory means;

(c) said translator static RAM memory means for connecting said processor means and said resources means while operating under control of said first, second and third state machines and said programmable array logic counter means and providing said means for accumulating said single 48-bit word and said four 48-bit word messages.

3. A message transfer system for accommodating message transfers between digital units operating on different message protocols and different clock rates comprising:

(a) first digital means for sending and receiving message data using one single 48-bit word message per message transfer cycle, said first digital means using an "x" MHz clock rate;

(b) second digital means for sending and receiving message data using a four 48-bit word message per message transfer cycle, said second digital means using a "y" MHz clock rate;

(c) translation means connecting said first digital means and said second digital means and including;

(c1) means for receiving message data derived from said first digital means for compatible delivery to said second digital means;

(c2) means for receiving said four 48-bit word messages from said second digital means for compatible delivery to said first digital means;

(c3) wherein said means for receiving message data from said second digital means includes;

(c3a) dual system bus means providing a first and second duplicate redundant bus for data transfer operations;

(c4) means to discard a request for word message transfer from said second digital means when said first digital means has a request for word message transfer uncompleted and still pending to said second digital means, said means including;

(c4a) a message status register which indicates the status of each request for word transfer as being completed or still incomplete.