Method of making power device with buffered gate shield region

• US 5,445,978 A
• Filed: 05/13/1994
• Issued: 08/29/1995
• Est. Priority Date: 04/23/1992
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Yilmaz, Hamza
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): MULPURI, SAVITRI
• Application Number:
  US08/242,519
• Time in Patent Office: 473 Days
• Field of Search: 437/41, 437/154, 437/27-30, 257/294, 257/328, 257/337, 257/340, 257/341
• US Class Current: 438/454
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

The present invention provides a gate buffer region between a gate shield region and active cells of a power device. This gate buffer region may, for example, be a relatively narrow, strip-like doped region which extends into an epitaxial layer from an upper surface of the epitaxial layer. The gate shield region is connected to a source electrode of the power device via a relatively high impedance connection. The gate buffer region, on the other hand, is connected to the source electrode with a relatively low impedance connection. This relatively low impedance connection may, for example, be a substantially direct metallized connection from a metal source electrode to the gate buffer region at the surface of the epitaxial layer.

Claims

1. A method of preventing failure of active cells adjacent a gate shield region, said gate shield region extending into a semiconductor body from an upper surface of said semiconductor body, said gate shield region being disposed at least partly underneath a gate pad and having insulation between said gate pad and said gate shield region, comprising:

forming a gate buffer region such that said gate buffer region exists between said active cells and said gate shield region, said gate buffer region extending into said semiconductor body from said upper surface of said semiconductor body, said gate buffer region being laterally spaced from both said gate shield region and said active cells.

2. The method of claim 1, wherein said active cells have a source electrode, further comprising:

forming an electrical connection between said source electrode and said gate buffer region so that said source electrode couples to said gate buffer region at said upper surface of said semiconductor body.

3. The method of claim 2, wherein said electrical connection between said source electrode and said gate buffer region has a first impedance, further comprising:

forming an electrical connection between said source electrode and said gate shield region, said electrical connection between said source electrode and said gate shield region having a second impedance, said first impedance being significantly smaller than said second impedance.

4. The method of claim 3, wherein said gate buffer region has a narrow substantially strip-like shape.

5. The method of claim 1, wherein said gate shield region extends into said semiconductor body to substantially the same depth that said gate buffer region extends into said semiconductor body.

6. The method of claim 1, wherein said gate buffer region is doped with a P type dopant to a doping concentration within the range of 1E18 cm^-3 -5E19 cm^-3.