Post processing shielding

• US 5,446,243 A
• Filed: 02/23/1994
• Issued: 08/29/1995
• Est. Priority Date: 05/20/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Rippens, Roger A., Crowder, George
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): Figlin, Cheryl R.
• Application Number:
  US08/209,355
• Time in Patent Office: 552 Days
• Field of Search: 174/250, 174/262, 174/264, 174/266, 361/784, 361/792
• US Class Current: 174/250
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0218 by printed shielding conductors, ground planes or power plane H05K1/0236 takes precedence
• CPC Class Codes: H05K 1/0219 Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors

Abstract

A system and method for reducing coupled noise in a multilayer circuit board having signal lines disposed within a set of wiring channels on each of a plurality of the layers; and, a vias disposed within a set of via channels. According to a first embodiment, otherwise unused vias traverse the layers and are connected with otherwise unused signal lines to form electrical nets, thus reducing coupled noise throughout the module. In the context of the above-described environment, a method for reducing coupled noise includes the steps of determining the locations of unused ones of the wiring channels and unused ones of the via channels; providing shield lines disposed within the unused wiring channels and unused via channels; and, interconnecting the shield lines with one another and to a reference voltage by way of at least one terminating resistance.

Claims

1. A method for reducing coupled noise in a multilayer circuit board having a plurality of signal lines disposed within a set of wiring channels on each of a plurality of layers, the wiring channels being greater in number than the number of signal lines;

and, a plurality of vias disposed within a set of via channels and traversing the layers and connecting the signal lines into electrical nets, the via channels being greater in number than the number of bias;

said method for reducing coupled noise comprising the steps of;

determining the locations of unused ones of the wiring channels and unused ones of the via channels;

providing shield lines disposed within the unused wiring channels and unused via channels; and

,

electrically interconnecting the shield lines with one another and to a reference voltage so as to electromagnetically shield at least one of said nets.

2. The method of claim 1 wherein the step of electrically interconnecting comprises the further step of coupling the shield lines to a ground pin pad of each of a plurality of chips on the circuit board, each by way of a terminating resistance.

3. The method of claim 1 wherein the step of electrically interconnecting comprises the further step of electrically connecting the shield lines to a ground plane of the circuit board.

4. The method of claim 2 wherein the terminating resistance is no greater than 5 thousand ohms.

5. The method of claim 3 wherein the shield lines are connected to the ground plane by way of a terminating resistance of no greater than 5 thousand ohms.

6. A method for reducing coupled noise in a multilayer circuit board having a plurality of signal lines disposed within a set of fixed wiring channels on each of a plurality of layers, the wiring channels being greater in number than the number of signal lines;

and, a plurality of bias disposed within a set of fixed via channels and traversing the layers and connecting the signal lines into electrical nets, the via channels being greater in number than the number of vias;

said method for reducing coupled noise comprising the steps of;

determining the locations of unused ones of the wiring channels and unused ones of the via channels;

providing electromagnetic shield lines disposed within the unused wiring channels and unused via channels; and

,

interconnecting the shield lines with one another, to a ground plane of the circuit board and to a ground pin pad of each of a plurality of chips on the circuit board, each by way of a terminating resistance of no greater than 5 thousand ohms.