Test circuit for large scale integrated circuits on a wafer

• US 5,446,395 A
• Filed: 09/21/1993
• Issued: 08/29/1995
• Est. Priority Date: 09/22/1992
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Goto, Junichi
• Primary Examiner(s): Karlsen, Ernest F.
• Application Number:
  US08/124,071
• Time in Patent Office: 707 Days
• Field of Search: 324/158 R, 324/73.1, 324/763, 324/158.1, 371/22.5, 371/22.6
• US Class Current: 324/754.03
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test

Abstract

A test circuit for conducting a simultaneous test of a plurality of integrated circuits provided in dicing regions of a wafer. The test circuit has a pattern generator electrically connected to the integrated circuits through first interconnections for generating input signal patterns and subsequent transmission thereof to each of the integrated circuits and pattern compressor/comparator electrically connected to the integrated circuits through second interconnections for analyzing output signals fetched from the integrated circuits so as to conduct a simultaneous test of a plurality of the integrated circuits.

Claims

1. A circuit for simultaneously testing at least two of a plurality of integrated circuits provided in dicing regions of a wafer comprising:

an input test signal generating and transmitting means electrically connected to at least two of said plurality of integrated circuits through first interconnection means for generating input test signal patterns and for subsequently transmitting said input test signal patterns to each of said at least two integrated circuits; and

output test signal analyzing means directly electrically connected to each of said at least two integrated circuits through second interconnection means for analyzing output test signals output from each of said at least two integrated circuits in response to said input test signal patterns so as to conduct a test of each of said at least two integrated circuits simultaneously, a number of said analyzing means being equal to a number of integrated circuits to be simultaneously tested.

2. The circuit as claimed in claim 1, wherein said test circuit is provided outside said dicing regions in which said integrated circuits are provided.

3. The circuit as claimed in claim 1, further comprising clock signal generating and transmission means connected to said at least two integrated circuits through third interconnections means for generating clock signals and for subsequently transmitting said clock signals to each of said at least two integrated circuits.

4. The circuit as claimed in claim 1, wherein said analyzing means comprise means for compressing a time series of said output signal patterns output from each of said at least two integrated circuits and means for comparing said compressed signals with expected values to determine whether said compressed signals and said expected values match.