Noise tolerant code setting circuit
First Claim
1. A code setting circuit comprising:
- a plurality of pad terminals to each of which a voltage pulse is applied;
a plurality of thin-film resistors corresponding respectively to the pad terminals, each of said thin-film resistors being connected between the corresponding pad terminal and a reference potential;
a plurality of first transistors of first conductivity type adapted to be rendered conductive in response to a turn-on pulse;
a plurality of second transistors of the first conductivity type corresponding to said first transistors, each of the second transistors having a channel connected in parallel with a channel of the corresponding first transistor between a voltage source and a corresponding one of a plurality of nodes;
a plurality of inverters corresponding respectively to the second transistors and the nodes, each of the inverters being connected between the corresponding node and the gate terminal of the corresponding second transistor;
a plurality of third transistors of second conductivity type opposite to the first conductivity type and corresponding respectively to said nodes, each of the third transistors having a channel connected at one end to the corresponding node and a gate terminal biased so that the third transistor prevents said voltage source from being coupled through a corresponding one of the second transistors to a corresponding one of said pad terminals;
a plurality of blocking means respectively corresponding to said third transistors and said pad terminals, each of the blocking means being connected between the other end of the channel of the corresponding third transistor and the corresponding pad terminal for preventing a noise pulse which is generated when said voltage pulse is applied to the corresponding pad terminal from being applied to the corresponding third transistor; and
means for generating a digital signal corresponding to a set of different potentials developed at said nodes.
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Accused Products
Abstract
In a code setting circuit wherein pad terminals are supplied with a voltage pulse to burn out corresponding thin-film resistors, first transistors of first conductivity type are adapted to be turned on in response to a turn-on pulse and second transistors of the first conductivity type are provided. The channel of each second transistor is connected in parallel with the channel of each first transistor between a voltage source and one of circuit nodes at which desired potentials are developed and a digital setting signal is generated corresponding thereto. Inverters are connected between the nodes and the gate terminals of the second transistors to keep the nodes at the desired potentials. Third transistors of second conductivity type are provided to prevent the voltage source from being coupled through the second transistors to the pad terminals. Blocking means are provided respectively corresponding to the third transistors and the pad terminals. Each blocking means is connected between the other end of the channel of the corresponding third transistor and the corresponding pad terminal for preventing a noise pulse generated when the voltage pulse is applied to the corresponding pad terminal from being applied to the corresponding third transistor.
17 Citations
4 Claims
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1. A code setting circuit comprising:
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a plurality of pad terminals to each of which a voltage pulse is applied; a plurality of thin-film resistors corresponding respectively to the pad terminals, each of said thin-film resistors being connected between the corresponding pad terminal and a reference potential; a plurality of first transistors of first conductivity type adapted to be rendered conductive in response to a turn-on pulse; a plurality of second transistors of the first conductivity type corresponding to said first transistors, each of the second transistors having a channel connected in parallel with a channel of the corresponding first transistor between a voltage source and a corresponding one of a plurality of nodes; a plurality of inverters corresponding respectively to the second transistors and the nodes, each of the inverters being connected between the corresponding node and the gate terminal of the corresponding second transistor; a plurality of third transistors of second conductivity type opposite to the first conductivity type and corresponding respectively to said nodes, each of the third transistors having a channel connected at one end to the corresponding node and a gate terminal biased so that the third transistor prevents said voltage source from being coupled through a corresponding one of the second transistors to a corresponding one of said pad terminals; a plurality of blocking means respectively corresponding to said third transistors and said pad terminals, each of the blocking means being connected between the other end of the channel of the corresponding third transistor and the corresponding pad terminal for preventing a noise pulse which is generated when said voltage pulse is applied to the corresponding pad terminal from being applied to the corresponding third transistor; and means for generating a digital signal corresponding to a set of different potentials developed at said nodes. - View Dependent Claims (2, 3, 4)
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Specification