Digital signal processing system

• US 5,446,456 A
• Filed: 12/29/1993
• Issued: 08/29/1995
• Est. Priority Date: 04/30/1993
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Seo, Jin-gyo
• Primary Examiner(s): Young, Brian K.
• Application Number:
  US08/175,279
• Time in Patent Office: 608 Days
• Field of Search: 341/118, 341/119, 341/94, 348/607, 348/603, 348/610, 371/31
• US Class Current: 341/118
• CPC Class Codes: H04N 19/527 Global motion vector estimation
• CPC Class Codes: H04N 19/86 involving reduction of coding artifacts, e.g. of blockiness
• CPC Class Codes: H04N 19/895 in combination with error concealment

Abstract

A digital signal processing system error-correction-decodes received or reproduced data, and compensates the error-correction-decoded data according to an amount of motion which is generated between sequential frames, in order to restore the received or reproduced data into an original video signal. The digital signal processing system includes an error concealment unit which outputs a video signal of a current frame if the decoded data is error-corrected data, and substitutes the current frame data at the current frame position with the previous frame data at the position corresponding to the amount of motion if the decoded data is data of an area where the error is not corrected, thereby providing a high quality picture without degradation.

Claims

1. A digital signal processing system comprising:

error-correction-decoder means for error-correction-decoding data for generating an error flag for errors beyond an error correction capability;

data restoring means for compensating motion of the error-correction-decoded data according to a motion signal which is generated between sequential frames for restoring the error-correction-decoded data into an original video signal; and

error concealment means for replacing a video signal for an area where the error is not corrected among the error-correction-decoded data with a previous frame video signal,

wherein the error concealment means comprises;

a first frame memory for storing luminance data output from the data restoring means in frame units;

a second frame memory for storing color data output from the data restoring means in frame units;

selection means for selecting outputs of the first and second frame memories or the data restoring means responsive to an error flag output from the error-correction-decoder means; and

address generation means for generating an address obtained by adding a position corresponding to the motion signal to a current frame position or an address of the current frame position responsive to the error flag and for outputting the address generated as an address signal of the first and second frame memories.

2. The digital signal processing system according to claim 1 comprising a contour compensation filter for filtering a contour portion of the area substituted in order to reduce a block effect when the signal output from the selection means is substituted with the previous frame video signal.

3. The digital signal processing system according to claim 2 wherein the address generation means comprises:

a first address generator for generating the addresses of the first and second frame memories;

a second address generator for generating an address by adding an address of a position corresponding to the motion signal to an address of the current frame position generated in the first address generator; and

an address selector for selecting an address generated in the first or second address generators responsive to the error flag and supplying an address selected as addresses of the first and second frame memories.

4. The digital signal processing system according to claim 3 wherein the second address generator comprises:

a frame memory for storing the motion signal output from the data restoring means in frame units;

an address generator for the motion signal which generates a write address and a read address of the frame memory; and

an adder for adding an output of the first address generator to the output of the frame memory.

5. The digital signal processing system according to claim 4 wherein the address selector selects the output of the adder only when a current mode is a motion video mode and the error flag is generated.

6. A digital signal processing system comprising:

an error correction decoder receiving digital picture data for error correcting the digital picture data, for outputting corrected data responsive to the error correcting, and for outputting an error flag when errors in the digital picture data cannot be corrected;

a data restorer coupled to the error correction decoder for expanding and post processing the corrected data, for compensating the corrected data according to an amount of motion generated between sequential frames, for restoring the corrected data into video data, and for outputting a motion vector indicative of the amount of motion; and

an error concealer coupled to the data restorer and to the error correction decoder for outputting the video data when the digital picture data corresponding to a current picture can be corrected, and for replacing the video data corresponding to the current picture at a current picture position with previous video data corresponding to the current picture position adjusted by the motion vector when an error is indicated by the error flag.