Apparatus for recovering data and clock information from an encoded serial data stream

• US 5,446,765 A
• Filed: 08/17/1994
• Issued: 08/29/1995
• Est. Priority Date: 11/19/1992
• Status: Expired due to Fees

• Current Assignee: Cirrus Logic International Ltd (Cirrus Logic Incorporated)
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Leger, Geary L.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Le, Amanda T.
• Application Number:
  US08/292,629
• Time in Patent Office: 377 Days
• Field of Search: 375/55, 375/75, 375/80, 375/83, 375/87, 375/110, 375/56, 375/60, 375/84, 341/68, 341/70, 341/71, 371/37.4, 307/269, 307/601, 307/602, 328/55, 328/63, 327/141, 327/161, 327/261, 327/291
• US Class Current: 375/359
• CPC Class Codes: G11B 20/1419 to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
• CPC Class Codes: H03M 5/12 Biphase level code, e.g. split phase code, Manchester code; Biphase space or mark code, e.g. double frequency code
• CPC Class Codes: H04L 25/4904 using self-synchronising codes, e.g. split-phase codes

Abstract

The invention doubles the bit rate for a given media bandwidth as compared to, for example, Manchester encoding. It is applicable to serial transmission or storage of digital data. An arbitrary NRZ data stream is first encoded by a pre-encoding method, such as Manchester, that combines clock and data to represent a single NRZ bit in one clock cycle. A toggle flip flop then re-encodes the pre-encoded waveform, thus generating a double toggle (DT) encoded waveform, which spreads the spectral energy over a larger bandwidth and encodes two NRZ data bits within one transmission clock cycle. In the case of Manchester pre-encoding, data is decoded by determining if there are transitions nearly synchronous with an edge of the recovered clock. For other pre-encoding methods, decoded data is determined by the length of the transition period and the edge polarity of the recovered clock at the leading edge of the transition within the DT encoded waveform. DC offset is reduced by substitution within and inversion of the DT encoded waveform. DC offset compensation of the encoded waveform is either removed prior to data decoding or after a data pre-decoding step; in either case the apparatus searches and detects predetermined substituted patterns in order to correct for the inversion or substitution. Further, a clock state generator is disclosed that uses precision silicon delays in order to generate clock states and quickly synchronize the states to the received encoded waveform. The clock states generate the recovered clocks required to decode data from the encoded waveform.

Claims

1. A clock recovery apparatus to output a recovered clock from a serial signal containing both clock information and data information, comprising:

transition detector means to detect transitions in said serial signal and to generate a transition-detected signal responsive to said transitions;

first odd clock state generator means, including a first and a second precision delay means, and being responsive to said transition-detected signal and to a clock-state-four signal, to generate a clock-state-one signal that, in the absence of said transitions, is held active by said first precision delay means for a predetermined duration starting immediately after said clock-state-four signal;

first even clock state generator means, including a third precision delay means, and being responsive to said clock-state-one signal, to generate a clock-state-two signal that is held active by said third precision delay means for said predetermined duration starting immediately after said clock-state-one signal;

second odd clock state generator means, including a fourth and a fifth precision delay means, and being responsive to said transition-detected signal and to said clock-state-two signal, to generate a clock-state-three signal that, in the absence of said transitions, is held active by said fourth precision delay means for said predetermined period starting immediately after said clock-state-two signal;

second even clock state generator means, including a sixth precision delay means, and being responsive to said clock-state-three signal, to generate said clock-state-four signal that is held active by said sixth precision delay means for said predetermined duration starting immediately after said clock-state-three signal;

recovered clock output means to generate and to output said recovered clock responsive to one or more of said clock-state-one, clock-state-two, clock-state-three, and clock-state-four signals;

said second precision delay means, operating when said transition-detected signal occurs close to the start of said clock-state-one signal, to hold said clock-state-one signal active for said predetermined duration after said occurrence of said transition-detected signal, notwithstanding the operation of said first precision delay, such that when said transition-detected signal occurs during said clock-state-one signal then the duration of said clock-state-one signal is lengthened so as to correspond to the phase of said serial signal and when said transition-detected signal occurs prior to the start of said clock-state-one signal then said clock-state-one signal is immediately started so as to correspond to the phase of said serial signal;

said fifth precision delay means, operating when said transition-detected signal occurs close to the start of said clock-state-three signal, to hold said clock-state-three signal active for said predetermined duration after said occurrence of said transition-detected signal, notwithstanding the operation of said fourth precision delay, such that when said transition-detected signal occurs during said clock-state-three signal then the duration of said clock-state-three signal is lengthened so as to correspond to the phase of said serial signal and when said transition-detected signal occurs prior to the start of said clock-state-three signal then said clock-state-three signal is immediately started so as to correspond to the phase of said serial signal.

2. A clock recovery apparatus to output a recovered clock from a serial signal containing both clock information and data information and beginning with a predetermined phase-sensitive preamble, comprising:

transition detector means to detect transitions in said serial signal and to generate a transition-detected signal responsive to said transitions;

first odd clock state generator means, including a first and a second precision delay means, and being responsive to said transition-detected signal and to a clock-state-four signal, to generate a clock-state-one signal that, in the absence of said transitions, is held active by said first precision delay means for a predetermined duration starting immediately after said clock-state-four signal;

first even clock state generator means, including a third precision delay means, and being responsive to said clock-state-one signal, to generate a clock-state-two signal that is held active by said third precision delay means for said predetermined duration starting immediately after said clock-state-one signal;

second odd clock state generator means, including a fourth and a fifth precision delay means, and being responsive to said transition-detected signal and to said clock-state-two signal, to generate a clock-state-three signal that, in the absence of said transitions, is held active by said fourth precision delay means for said predetermined period starting immediately after said clock-state-two signal;

second even clock state generator means, including a sixth precision delay means, and being responsive to said clock-state-three signal, to generate said clock-state-four signal that is held active by said sixth precision delay means for said predetermined duration starting immediately after said clock-state-three signal;

recovered clock output means to generate and to output said recovered clock responsive to one or more of said clock-state-one, clock-state-two, clock-state-three, and clock-state-four signals;

said second precision delay means, operating when said transition-detected signal occurs close to the start of said clock-state-one signal, to hold said clock-state-one signal active for said predetermined duration after said occurrence of said transition-detected signal, notwithstanding the operation of said first precision delay, such that when said transition-detected signal occurs during said clock-state-one signal then the duration of said clock-state-one signal is lengthened so as to correspond to the phase of said serial signal and when said transition-detected signal occurs prior to the start of said clock-state-one signal then said clock-state-one signal is immediately started so as to correspond to the phase of said serial signal;

said fifth precision delay means, operating when said transition-detected signal occurs close to the start of said clock-state-three signal, to hold said clock-state-three signal active for said predetermined duration after said occurrence of said transition-detected signal, notwithstanding the operation of said fourth precision delay, such that when said transition-detected signal occurs during said clock-state-three signal then the duration of said clock-state-three signal is lengthened so as to correspond to the phase of said serial signal and when said transition-detected signal occurs prior to the start of said clock-state-three signal then said clock-state-three signal is immediately started so as to correspond to the phase of said serial signal;

a polarity flipping means to flip the polarity of said recovered clock responsive to misalignment between the occurrence of said predetermined phase-sensitive preamble and the polarity of said recovered clock, wherein said misalignment is detected when either said clock-state-one or said clock-state-three decodes a predetermined binary pattern from said preamble.

3. A clock recovery apparatus to output a recovered clock from a serial signal containing both clock and data information and beginning with a predetermined phase-sensitive preamble, comprising:

transition detector means to detect transitions in said serial signal and to generate a transition-detected signal responsive to said transitions;

first odd clock state generator means, including a first and a second precision delay means, and being responsive to said transition-detected signal, to a flip signal, and to a clock-state-four signal, to generate a clock-state-one signal that, in the absence of said transitions, is held active by said first precision delay means for a predetermined duration starting immediately after said clock-state-four signal;

first even clock state generator means, including a third precision delay means, and being responsive to said clock-state-one signal, to generate a clock-state-two signal that is held active by said third precision delay means for said predetermined duration starting immediately after said clock-state-one signal;

second odd clock state generator means, including a fourth and a fifth precision delay means, and being responsive to said transition-detected signal, to said flip signal, and to said clock-state-two signal, to generate a clock-state-three signal that, in the absence of said transitions, is held active by said fourth precision delay means for said predetermined period starting immediately after said clock-state-two signal;

second even clock state generator means, including a sixth precision delay means, and being responsive to said clock-state-three signal, to generate said clock-state-four signal that is held active by said sixth precision delay means for said predetermined duration starting immediately after said clock-state-three signal;

recovered clock output means to generate and to output said recovered clock responsive to one or more of said flip, clock-state-one, clock-state-two, clock-state-three, and clock-state-four signals;

said second precision delay means, operating when said transition-detected signal occurs close to the start of said clock-state-one signal, to hold said clock-state-one signal active for said predetermined duration after said occurrence of said transition-detected signal, notwithstanding the operation of said first precision delay, such that when said transition-detected signal occurs during said clock-state-one signal then the duration of said clock-state-one signal is lengthened so as to correspond to the phase of said serial signal and when said transition-detected signal occurs prior to the start of said clock-state-one signal then said clock-state-one signal is immediately started so as to correspond to the phase of said serial signal;

said fifth precision delay means, operating when said transition-detected signal occurs close to the start of said clock-state-three signal, to hold said clock-state-three signal active for said predetermined duration after said occurrence of said transition-detected signal, notwithstanding the operation of said fourth precision delay, such that when said transition-detected signal occurs during said clock-state-three signal then the duration of said clock-state-three signal is lengthened so as to correspond to the phase of said serial signal and when said transition-detected signal occurs prior to the start of said clock-state-three signal then said clock-state-three signal is immediately started so as to correspond to the phase of said serial signal;

a polarity flipping means to flip the polarity of said recovered clock and to generate said flip signal, responsive to misalignment between the occurrence of said predetermined phase-sensitive preamble and the polarity of said recovered clock, wherein said misalignment is detected when either said clock-state-one or said clock-state-three decodes a predetermined binary pattern from said preamble, said first odd clock state generator means, said second odd clock state generator means, and said recovered clock output means responsive to the occurrence of said flip signal so as to invert the polarity of said recovered clock.

4. An apparatus for decoding a non-return-to-zero (NRZ) data stream from a serial signal, beginning with a predetermined phase-sensitive preamble, comprising:

transition detector means to detect transitions in said serial signal and to generate a transition-detected signal responsive to said transitions;

first odd clock state generator means, including a first and a second precision delay means, and being responsive to said transition-detected signal and to a clock-state-four signal, to generate a clock-state-one signal that, in the absence of said transitions, is held active by said first precision delay means for a predetermined duration starting immediately after said clock-state-four signal;

first even clock state generator means, including a third precision delay means, and being responsive to said clock-state-one signal, to generate a clock-state-two signal that is held active by said third precision delay means for said predetermined duration starting immediately after said clock-state-one signal;

second odd clock state generator means, including a fourth and a fifth precision delay means, and being responsive to said transition-detected signal and to said clock-state-two signal, to generate a clock-state-three signal that, in the absence of said transitions, is held active by said fourth precision delay means for said predetermined period starting immediately after said clock-state-two signal;

second even clock state generator means, including a sixth precision delay means, and being responsive to said clock-state-three signal, to generate said clock-state-four signal that is held active by said sixth precision delay means for said predetermined duration starting immediately after said clock-state-three signal;

recovered clock output means to generate and to output said recovered clock, having a half bit period and indicating the timing of transitions within said serial signal, responsive to one or more of said clock-state-one, clock-state-two, clock-state-three, and clock-state-four signals;

said second precision delay means, operating when said transition-detected signal occurs close to the start of said clock-state-one signal, to hold said clock-state-one signal active for said predetermined duration after said occurrence of said transition-detected signal, notwithstanding the operation of said first precision delay, such that when said transition-detected signal occurs during said clock-state-one signal then the duration of said clock-state-one signal is lengthened so as to correspond to the phase of said serial signal and when said transition-detected signal occurs prior to the start of said clock-state-one signal then said clock-state-one signal is immediately started so as to correspond to the phase of said serial signal;

said fifth precision delay means, operating when said transition-detected signal occurs close to the start of said clock-state-three signal, to hold said clock-state-three signal active for said predetermined duration after said occurrence of said transition-detected signal, notwithstanding the operation of said fourth precision delay, such that when said transition-detected signal occurs during said clock-state-three signal then the duration of said clock-state-three signal is lengthened so as to correspond to the phase of said serial signal and when said transition-detected signal occurs prior to the start of said clock-state-three signal then said clock-state-three signal is immediately started so as to correspond to the phase of said serial signal;

a polarity flipping means to flip the polarity of said recovered clock responsive to misalignment between the occurrence of said predetermined phase-sensitive preamble and the polarity of said recovered clock, wherein said misalignment is detected when either said clock-state-one or said clock-state-three decodes a predetermined binary pattern from said preamble;

pre-decoder means to generate a preliminary decoded data stream responsive to said serial signal and to said recovered clock;

offset replacement decoder means, coupled to said recovered clock output means and said predecoder means, responsive to said preliminary decoded data stream, said serial signal, and said recovered clock, to generate said NRZ data stream from said preliminary decoded data stream by detecting predetermined substituted transition patterns within said serial signal by detecting a predetermined sequential number of half bit periods with no transition and, when detected, correcting said preliminary decoded data stream to produce said NRZ data stream.

5. An apparatus in accordance with claim 4, wherein said offset replacement decoder means detects said predetermined substituted transition patterns within said serial signal having at least five of said half bit periods of the same value and corrects said preliminary decoded data stream by changing the value of a single bit to generate said NRZ data stream.

8. The apparatus of any of claims 4 to 7 wherein,

said pre-decoder means decodes said serial signals encoded by a Manchester pre-encoding means,

in the case where a transition of said serial signal synchronizes with said recovered clock, said pre-decoder means generates a one within said preliminary decoded data stream, and

in the case where no transition of said serial signal synchronizes with said recovered clock, said pre-decoder means generates a zero within said preliminary decoded data stream.

9. The apparatus of any of claims 4 to 7 wherein,

said pre-decoder means decodes said serial signals encoded by a Biphase-Level pre-encoding means,

in the case where a transition of said serial signal synchronizes with said recovered clock, said pre-decoder generates a zero within said preliminary decoded data stream, and

in the case where no transition of said serial signal synchronizes with said recovered clock, said pre-decoder generates a one within said preliminary decoded data stream.

6. An apparatus for decoding a non-return-to-zero (NRZ) data stream from a serial signal, beginning with a predetermined phase-sensitive preamble, received from a local area network, comprising:

transition detector means to detect transitions in said serial signal and to generate a transition-detected signal responsive to said transitions;

first odd clock state generator means, including a first and a second precision delay means, and being responsive to said transition-detected signal and to a clock-state-four signal, to generate a clock-state-one signal that, in the absence of said transitions, is held active by said first precision delay means for a predetermined duration starting immediately after said clock-state-four signal;

first even clock state generator means, including a third precision delay means, and being responsive to said clock-state-one signal, to generate a clock-state-two signal that is held active by said third precision delay means for said predetermined duration starting immediately after said clock-state-one signal;

second odd clock state generator means, including a fourth and a fifth precision delay means, and being responsive to said transition-detected signal and to said clock-state-two signal, to generate a clock-state-three signal that, in the absence of said transitions, is held active by said fourth precision delay means for said predetermined period starting immediately after said clock-state-two signal;

second even clock state generator means, including a sixth precision delay means, and being responsive to said clock-state-three signal, to generate said clock-state-four signal that is held active by said sixth precision delay means for said predetermined duration starting immediately after said clock-state-three signal;

recovered clock output means to generate and to output said recovered clock, having a half bit period and indicating the timing of transitions within said serial signal received from said local area network, responsive to one or more of said clock-state-one, clock-state-two, clock-state-three, and clock-state-four signals;

said second precision delay means, operating when said transition-detected signal occurs close to the start of said clock-state-one signal, to hold said clock-state-one signal active for said predetermined duration after said occurrence of said transition-detected signal, notwithstanding the operation of said first precision delay, such that when said transition-detected signal occurs during said clock-state-one signal then the duration of said clock-state-one signal is lengthened so as to correspond to the phase of said serial signal and when said transition-detected signal occurs prior to the start of said clock-state-one signal then said clock-state-one signal is immediately started so as to correspond to the phase of said serial signal;

said fifth precision delay means, operating when said transition-detected signal occurs close to the start of said clock-state-three signal, to hold said clock-state-three signal active for said predetermined duration after said occurrence of said transition-detected signal, notwithstanding the operation of said fourth precision delay, such that when said transition-detected signal occurs during said clock-state-three signal then the duration of said clock-state-three signal is lengthened so as to correspond to the phase of said serial signal and when said transition-detected signal occurs prior to the start of said clock-state-three signal then said clock-state-three signal is immediately started so as to correspond to the phase of said serial signal;

a polarity flipping means to flip the polarity of said recovered clock responsive to misalignment between the occurrence of said predetermined phase-sensitive preamble and the polarity of said recovered clock, wherein said misalignment is detected when either said clock-state-one or said clock-state-three decodes a predetermined binary pattern from said preamble;

pre-decoder means to generate a preliminary decoded data stream responsive to said serial signal and to said recovered clock;

offset replacement decoder means, coupled to said recovered clock output means and said predecoder means, responsive to said preliminary decoded data stream, said serial signal, and said recovered clock, to generate and output said NRZ data stream from said preliminary decoded data stream by detecting predetermined substituted transition patterns within said serial signal by detecting a predetermined sequential number of half bit periods with no transition and when detected, correcting said preliminary decoded data stream prior to its being output as said NRZ data stream.

7. An apparatus in accordance with claim 6, wherein said offset replacement decoder means detects said predetermined substituted transition patterns within said serial signal having at least five of said half bit periods of the same value and corrects said preliminary decoded data stream by changing the value of a single bit to generate said NRZ data stream.

10. An apparatus for decoding a non-return-to-zero (NRZ) data stream from a serial signal, beginning with a predetermined phase-sensitive preamble, comprising:

transition detector means to detect transitions in said serial signal and to generate a transition-detected signal responsive to said transitions;

first odd clock state generator means, including a first and a second precision delay means, and being responsive to said transition-detected signal and to a clock-state-four signal, to generate a clock-state-one signal that, in the absence of said transitions, is held active by said first precision delay means for a predetermined duration starting immediately after said clock-state-four signal;

first even clock state generator means, including a third precision delay means, and being responsive to said clock-state-one signal, to generate a clock-state-two signal that is held active by said third precision delay means for said predetermined duration starting immediately after said clock-state-one signal;

second odd clock state generator means, including a fourth and a fifth precision delay means, and being responsive to said transition-detected signal and to said clock-state-two signal, to generate a clock-state-three signal that, in the absence of said transitions, is held active by said fourth precision delay means for said predetermined period starting immediately after said clock-state-two signal;

second even clock state generator means, including a sixth precision delay means, and being responsive to said clock-state-three signal, to generate said clock-state-four signal that is held active by said sixth precision delay means for said predetermined duration starting immediately after said clock-state-three signal;

recovered clock output means to generate and to output said recovered clock, having a half bit period and indicating the timing of transitions within said serial signal, responsive to one or more of said clock-state-one, clock-state-two, clock-state-three, and clock-state-four signals;

said second precision delay means, operating when said transition-detected signal occurs close to the start of said clock-state-one signal, to hold said clock-state-one signal active for said predetermined duration after said occurrence of said transition-detected signal, notwithstanding the operation of said first precision delay, such that when said transition-detected signal occurs during said clock-state-one signal then the duration of said clock-state-one signal is lengthened so as to correspond to the phase of said serial signal and when said transition-detected signal occurs prior to the start of said clock-state-one signal then said clock-state-one signal is immediately started so as to correspond to the phase of said serial signal;

said fifth precision delay means, operating when said transition-detected signal occurs close to the start of said clock-state-three signal, to hold said clock-state-three signal active for said predetermined duration after said occurrence of said transition-detected signal, notwithstanding the operation of said fourth precision delay, such that when said transition-detected signal occurs during said clock-state-three signal then the duration of said clock-state-three signal is lengthened so as to correspond to the phase of said serial signal and when said transition-detected signal occurs prior to the start of said clock-state-three signal then said clock-state-three signal is immediately started so as to correspond to the phase of said serial signal;

a polarity flipping means to flip the polarity of said recovered clock responsive to misalignment between the occurrence of said predetermined phase-sensitive preamble and the polarity of said recovered clock, wherein said misalignment is detected when either said clock-state-one or said clock-state-three decodes a predetermined binary pattern from said preamble;

offset replacement decoder means, coupled to said recovered clock output means, responsive to said serial signal and said recovered clock, to generate a corrected encoded data stream by detecting predetermined substituted transition patterns within said serial signal by detecting a predetermined sequential number of half bit periods with no transition and when detected, correcting said serial signal prior to its being output as said corrected encoded data stream;

data decoder means to generate said NRZ data stream responsive to said corrected encoded data stream and to said recovered clock.

11. An apparatus in accordance with claim 10, wherein said offset replacement decoder means detects said predetermined substituted transition patterns within said serial signal having a sequence of at least five of said half bit periods all of the same value, corrects said serial signal into said corrected encoded data stream by inverting said serial signal after the first two half bit periods within said sequence of half bit periods.

14. The apparatus of any of claims 10 to 13 wherein,

said data decoder means decodes said serial signals encoded by Biphase-Mark (FM1) pre-encoding means,

in the case where the leading edge of a transition pattern within said corrected encoded data stream aligns with the rising edge of said recovered clock, when said transition pattern is four half bit periods all having the same value, then said data decoder means generates two zero bits within said NRZ data stream, when said transition pattern is two half bit periods all having the same value, then said data decoder means generates a single one bit within said NRZ data stream, when said transition pattern is three half bit periods all having the same value, then said data decoder means generates a zero bit followed by a one bit within said NRZ data stream;

in the case where the leading edge of a transition pattern within said corrected encoded data stream aligns with the falling edge of said recovered clock, when said transition pattern is two half bit periods all having the same value, then said data decoder means generates a single one bit within said NRZ data stream, when said transition pattern is three half bit periods all having the same value, then said data decoder means generates a single zero bit within said NRZ data stream.

15. The apparatus of any of claims 10 to 13 wherein,

said data decoder means decodes said serial signals encoded by a Differential-Manchester pre-encoding means,

in the case where the leading edge of a transition pattern within said corrected encoded data stream aligns with the rising edge of said recovered clock, when said transition pattern is four half bit periods all having the same value, then said data decoder means generates two zero bits within said NRZ data stream, when said transition pattern is two half bit periods all having the same value, then said data decoder means generates a single one bit within said NRZ data stream, when said transition pattern is three half bit periods all having the same value, then said data decoder means generates a zero bit followed by a one bit within said NRZ data stream;

in the case where the leading edge of a transition pattern within said corrected encoded data stream aligns with the falling edge of said recovered clock, when said transition pattern is two half bit periods all having the same value, then said data decoder means decodes it into a single one bit within said NRZ data stream, when said transition pattern is three half bit periods all having the same value, then said data decoder means generates a single zero bit within said NRZ data stream.

16. The apparatus of any of claims 10 to 13 wherein,

said data decoder means decodes said serial signals encoded by a Biphase-Space (FM0) pre-encoding means,

in the case where the leading edge of a transition pattern within said corrected encoded data stream aligns with the rising edge of said recovered clock, when said transition pattern is four half bit periods all having the same value, then said data decoder means generates two one bits within said NRZ data stream, when said transition pattern is two half bit periods all having the same value, then said data decoder means generates a single zero bit within said NRZ data stream, when said transition pattern is three half bit periods all having the same value, then said data decoder means generates a one bit followed by a zero bit within said NRZ data stream;

in the case where the leading edge of a transition pattern within said corrected encoded data stream aligns with the falling edge of said recovered clock, when said transition pattern is two half bit periods all having the same value, then said data decoder means generates a single zero bit within said NRZ data stream, when said transition pattern is three half bit periods all having the same value, then said data decoder means generates a single one bit within said NRZ data stream.

17. The apparatus of any of claims 10 to 13 wherein,

said data decoder means decodes said serial signals encoded by a Differential-Biphase-Level pre-encoding means,

in the case where the leading edge of a transition pattern within said corrected encoded data stream aligns with the rising edge of said recovered clock, when said transition pattern is four half bit periods all having the same value, then said data decoder means generates two one bits within said NRZ data stream, when said transition pattern is two half bit periods all having the same value, then said data decoder means generates a single zero bit within said NRZ data stream, when said transition pattern is three half bit periods all having the same value, then said data decoder means generates a one bit followed by a zero bit within said NRZ data stream;

in the case where the leading edge of a transition pattern within said corrected encoded data stream aligns with the falling edge of said recovered clock, when said transition pattern is two half bit periods all having the same value, then said data decoder means generates a single zero bit within said NRZ data stream, when said transition pattern is three half bit periods all having the same value, then said data decoder means generates a single one bit within said NRZ data stream.

12. An apparatus for decoding a non-return-to-zero (NRZ) data stream from a serial signal, beginning with a predetermined phase-sensitive preamble, received from a local area network, comprising:

transition detector means to detect transitions in said serial signal and to generate a transition-detected signal responsive to said transitions;

first odd clock state generator means, including a first and a second precision delay means, and being responsive to said transition-detected signal and to a clock-state-four signal, to generate a clock-state-one signal that, in the absence of said transitions, is held active by said first precision delay means for a predetermined duration starting immediately after said clock-state-four signal;

first even clock state generator means, including a third precision delay means, and being responsive to said clock-state-one signal, to generate a clock-state-two signal that is held active by said third precision delay means for said predetermined duration starting immediately after said clock-state-one signal;

second odd clock state generator means, including a fourth and a fifth precision delay means, and being responsive to said transition-detected signal and to said clock-state-two signal, to generate a clock-state-three signal that, in the absence of said transitions, is held active by said fourth precision delay means for said predetermined period starting immediately after said clock-state-two signal;

second even clock state generator means, including a sixth precision delay means, and being responsive to said clock-state-three signal, to generate said clock-state-four signal that is held active by said sixth precision delay means for said predetermined duration starting immediately after said clock-state-three signal;

recovered clock output means to generate and to output said recovered clock, having a half bit period and indicating the timing of transitions within said serial signal, responsive to one or more of said clock-state-one, clock-state-two, clock-state-three, and clock-state-four signals;

said second precision delay means, operating when said transition-detected signal occurs close to the start of said clock-state-one signal, to hold said clock-state-one signal active for said predetermined duration after said occurrence of said transition-detected signal, notwithstanding the operation of said first precision delay, such that when said transition-detected signal occurs during said clock-state-one signal then the duration of said clock-state-one signal is lengthened so as to correspond to the phase of said serial signal and when said transition-detected signal occurs prior to the start of said clock-state-one signal then said clock-state-one signal is immediately started so as to correspond to the phase of said serial signal;

said fifth precision delay means, operating when said transition-detected signal occurs close to the start of said clock-state-three signal, to hold said clock-state-three signal active for said predetermined duration after said occurrence of said transition-detected signal, notwithstanding the operation of said fourth precision delay, such that when said transition-detected signal occurs during said clock-state-three signal then the duration of said clock-state-three signal is lengthened so as to correspond to the phase of said serial signal and when said transition-detected signal occurs prior to the start of said clock-state-three signal then said clock-state-three signal is immediately started so as to correspond to the phase of said serial signal;

a polarity flipping means to flip the polarity of said recovered clock responsive to misalignment between the occurrence of said predetermined phase-sensitive preamble and the polarity of said recovered clock, wherein said misalignment is detected when either said clock-state-one or said clock-state-three decodes a predetermined binary pattern from said preamble;

offset replacement decoder means, coupled to said recovered clock output means, responsive to said serial signal and said recovered clock, to generate a corrected encoded data stream by detecting predetermined substituted transition patterns within said serial signal by detecting a predetermined sequential number of half bit periods with no transition and when detected, correcting said serial signal prior to its being output as said corrected encoded data stream;

data decoder means to generate said NRZ data stream responsive to said corrected encoded data stream and to said recovered clock.

13. An apparatus in accordance with claim 12, wherein said offset replacement decoder means detects said predetermined substituted transition patterns within said serial signal having a sequence of at least five of said half bit periods all of the same value, corrects said serial signal into said corrected encoded data stream by inverting said serial signal after the first two half bit periods within said sequence of half bit periods.