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Apparatus for recovering data and clock information from an encoded serial data stream

  • US 5,446,765 A
  • Filed: 08/17/1994
  • Issued: 08/29/1995
  • Est. Priority Date: 11/19/1992
  • Status: Expired due to Fees
First Claim
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1. A clock recovery apparatus to output a recovered clock from a serial signal containing both clock information and data information, comprising:

  • transition detector means to detect transitions in said serial signal and to generate a transition-detected signal responsive to said transitions;

    first odd clock state generator means, including a first and a second precision delay means, and being responsive to said transition-detected signal and to a clock-state-four signal, to generate a clock-state-one signal that, in the absence of said transitions, is held active by said first precision delay means for a predetermined duration starting immediately after said clock-state-four signal;

    first even clock state generator means, including a third precision delay means, and being responsive to said clock-state-one signal, to generate a clock-state-two signal that is held active by said third precision delay means for said predetermined duration starting immediately after said clock-state-one signal;

    second odd clock state generator means, including a fourth and a fifth precision delay means, and being responsive to said transition-detected signal and to said clock-state-two signal, to generate a clock-state-three signal that, in the absence of said transitions, is held active by said fourth precision delay means for said predetermined period starting immediately after said clock-state-two signal;

    second even clock state generator means, including a sixth precision delay means, and being responsive to said clock-state-three signal, to generate said clock-state-four signal that is held active by said sixth precision delay means for said predetermined duration starting immediately after said clock-state-three signal;

    recovered clock output means to generate and to output said recovered clock responsive to one or more of said clock-state-one, clock-state-two, clock-state-three, and clock-state-four signals;

    said second precision delay means, operating when said transition-detected signal occurs close to the start of said clock-state-one signal, to hold said clock-state-one signal active for said predetermined duration after said occurrence of said transition-detected signal, notwithstanding the operation of said first precision delay, such that when said transition-detected signal occurs during said clock-state-one signal then the duration of said clock-state-one signal is lengthened so as to correspond to the phase of said serial signal and when said transition-detected signal occurs prior to the start of said clock-state-one signal then said clock-state-one signal is immediately started so as to correspond to the phase of said serial signal;

    said fifth precision delay means, operating when said transition-detected signal occurs close to the start of said clock-state-three signal, to hold said clock-state-three signal active for said predetermined duration after said occurrence of said transition-detected signal, notwithstanding the operation of said fourth precision delay, such that when said transition-detected signal occurs during said clock-state-three signal then the duration of said clock-state-three signal is lengthened so as to correspond to the phase of said serial signal and when said transition-detected signal occurs prior to the start of said clock-state-three signal then said clock-state-three signal is immediately started so as to correspond to the phase of said serial signal.

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