Multi-processor system having shared memory for storing the communication information used in communicating between processors

• US 5,446,841 A
• Filed: 06/15/1992
• Issued: 08/29/1995
• Est. Priority Date: 06/15/1991
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Sasaki, Keiichi, Okura, Hiroyuki, Kohda, Katsuya, Kitano, Masahiro, Takeda, Katsumi, Ohfusa, Yoshitaka
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): AN, MENG AI T
• Application Number:
  US07/898,688
• Time in Patent Office: 1,170 Days
• Field of Search: 395/800, 395/375, 395/425, 395/400, 395/200, 395/725, 395/325, 364/200, 364/900, 364/468, 340/825.02, 340/825.16
• US Class Current: 709/213
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox

Abstract

An information processing system comprises: plural processors; a shared memory connected to the plurality of processors for enabling communication between the processors; a unit disposed in the shared memory for storing information for specifying a processor connected thereto; and a unit for checking, when a first processor communicates with a second processor, whether or not the first and second processors are connected to the shared memory for direct access thereto by referring to the information storing means. A method of communication between processors used with a multiprocessor system, comprises the steps of: storing information for specifying a processor connected to the shared memory for direct access thereto in a predetermined register of the shared memory; feeding a communication instruction for instructing a first processor to communicate with a second processor via the shared memory; checking, in response to the communication instruction, whether or not the first and second processors are connected to the shared memory to enable direct access; storing communication information from the first processor in the shared memory, in response to confirmation that the first and second processors are connected to the shared memory; feeding a communication read interruption from the shared memory to the second processor; and reading out, in response to the communication read interruption, the communication information from the shared memory to feed the communication information to the second processor.

Claims

1. A method of communication between processors used with an information processing system having a plurality of processors and a plurality of shared memories connected to said plurality of processors, said method comprising the steps of:

storing information from a processor for specifying which of said plurality of processors is connected to said shared memories to be directly accessible from another processor, into register means when said system is started by turning on a power supply to said system, or when said system is started just after connection paths between said shared memories and said processors are changed;

feeding a communication instruction from one of said processors to a specified one of said shared memories for indicating that said one of said processors communicates with another processor via said specified shared memory;

checking said information stored in said register means by said specified shared memory, in response to said communication instruction, and confirming by said specified shared memory that said one processor and said another processor are connected to said specified shared memory such that said specified shared memory is directly accessible from either of said one processor and said another processor;

storing communication information from said one processor into a memory area of said specified shared memory, after confirming that said one processor and said another processor are connected to said specified shared memory such that said specified shared memory is directly accessible from either of said one processor and said another processor;

feeding a communication read interruption from said specified shared memory to said another processor; and

reading out, in response to said communication read interruption, said communication information from said memory area of said specified shared memory by said another processor and storing said communication information in a primary storage of said another processor.

2. An information processing system according to claim 1, wherein said shared memory recognizes that a processor connected to an associated I/O port or ports is ineffective when said processor is turned-off or reset.

3. An information processing system according to claim 2, wherein said information for specifying a processor includes an identification number of said processor and an identification number of said I/O port or ports to which said processor is connected, and when said information for specifying the processor is stored in said register means in said shared memory, said information is checked over all of said register means as to whether the identification numbers have already been stored in said register means, and if the identification numbers have been already stored in said register means, an abnormal termination is performed in said system.

4. A method of communication between processors used with an information processing system having a plurality of real processors and a shared memory connected to said plurality of processors, each of said real processors including therein a plurality of virtual processors, said method comprising the steps of:

storing information from one of said virtual processors for specifying which of said virtual processors in said real processors is connected to said shared memory to be directly accessible from another real processor, into register means when said system is started by turning on a power supply to said system, or when said system is started just after connection paths between said shared memory and said processors are changed;

feeding a communication instruction from one of said virtual processors in said plurality of real processors to said shared memory for indicating that said one virtual processor communicates with another of said virtual processors in said real processors via said shared memory;

checking said information stored in said register means by said shared memory, in response to said communication instruction, and confirming by said shared memory that said one virtual processor and said another virtual processor are connected to said shared memory such that said shared memory is directly accessible from either of said one virtual processor and said another virtual processor;

storing communication information from said one virtual processor into a memory area of said shared memory, after confirming that said one virtual processor and said another virtual processor are connected to said shared memory such that said shared memory is directly accessible from either of said one virtual processor and said another virtual processor;

feeding a communication read interruption from said shared memory to the real processor having said another virtual processor;

feeding said communication read interruption from said real processor having said another virtual processor to said another virtual processor; and

reading out, in response to said communication read interruption, said communication information from said memory area of said shared memory by said another virtual processor and storing said communication information in a primary storage of said another virtual processor.

5. An information processing system according to claim 4, wherein said shared memory recognizes that the real processor connected to an associated I/O port or ports is ineffective when said real processor is turned-off or reset.

6. An information processing system according to claim 5, wherein said information for specifying said virtual processor includes an identification number of said virtual processor and an identification number of the I/O port or ports to which said real processor having the virtual processor is connected, and when said information for specifying the virtual processor is stored in said register means in said shared memory, it is checked over all of said register means as to whether the identification numbers have been already stored in said register means, and if the identification numbers have been already stored in said register means, an abnormal termination is performed in said system.