Cross-cache-line compounding algorithm for scism processors

• US 5,446,850 A
• Filed: 07/27/1994
• Issued: 08/29/1995
• Est. Priority Date: 01/15/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Blaner, Bartholomew, Jeremiah, Thomas L.
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US08/281,321
• Time in Patent Office: 398 Days
• Field of Search: 395/375, 395/800, 395/250
• US Class Current: 712/215
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3808 for instruction reuse, e.g. trace cache, branch target cache
• CPC Class Codes: G06F 9/3812 with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3853 of compound instructions

Abstract

A system for compounding instructions across cache line boundaries transfers an instruction line from a relatively slow memory to a instruction compounding unit if there is a miss for an instruction in that line in the instruction cache. At the same time the numerically preceding instruction in cache is transferred to the instruction compounding unit and instructions from the two lines are compounded. If a numerically preceding cache line has been compounded with a cache line that has been deleted and then replaced, compounding tags for the numerically preceding cache line are deleted.

Claims

1. A data processing system in which instructions are transferred in blocks called instruction lines from a relatively low speed memory to a relatively high speed cache memory and from which cache memory instruction lines are fetched for execution and are deleted a line at a time, said system including an instruction compounding unit in which instructions are processed in order to generate tag information that indicates instructions that can be executed in parallel, said data processing system comprising in combination:

means to address a first instruction line in said cache memory in order to transfer said first instruction line from said cache memory to an instruction fetch unit;

means to generate a miss signal if said first instruction line is not resident in said high speed cache memory;

means responsive to said miss signal for transferring said first instruction line from said relatively low speed memory to said instruction compounding unit;

means responsive to said miss signal for determining an address of a second instruction line that is next in succession to said first instruction line for transfer to said instruction fetch unit;

means for transferring said second instruction line to said instruction compounding unit if said second instruction line resides in said cache memory;

said instruction compounding unit processing instructions from said first instruction line and said second instruction line in order to generate tag information indicating an instruction in said first instruction line that can be executed in parallel with an instruction in said second instruction line

means for determining if an instruction line in said cache memory has been deleted and replaced prior to its execution;

means to determine if said deleted and replaced instruction line contains instructions that have been compounded with another instruction line in said cache memory; and

means to delete tag information that indicates an instruction in said another instruction line can be compounded with an instruction in said instruction line that has been deleted and replaced.

2. A data processing system as in claim 1 wherein said second instruction line is transferred to said instruction compounding unit during an interval when said first instruction line is transferred from said relatively low speed memory to said instruction compounding unit.

3. A processing system as in claim 1, wherein said means for determining an address includes means to decrement the address of a missed instruction.

4. A processing system as in claim 1, wherein said means for determining an address includes means to decrement the address of a missed instruction.

5. A processing system as in claim 1, wherein said means for determining an address includes means to decrement the address of a missed instruction.