Processor adapted for sharing memory with more than one type of processor

• US 5,446,865 A
• Filed: 03/13/1990
• Issued: 08/29/1995
• Est. Priority Date: 03/13/1990
• Status: Expired due to Term

• Current Assignee: AT&T IPM Corp. (AT&T, Inc.)
• Original Assignee: AT&T Corporation (AT&T, Inc.)
• Inventors: Sufi, Akkas T., Fairfield, Robert C., Corcoran, Gary T.
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): An, Meng-Ai T.
• Application Number:
  US07/493,018
• Time in Patent Office: 1,995 Days
• Field of Search: 395/375, 395/500, 395/650, 395/425, 395/800, 395/400, 395/325
• US Class Current: 703/26
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set

Abstract

A processor specially adapted for use as a coprocessor. The processor is implemented as a microprocessor. The adaptations include the following: The microprocessor has a master-slave pin which receives an input which determines whether the microprocessor operates as a bus master or a bus slave. Certain output pins have three-state bus drivers which employ feedback to ensure that a signal on a line being even by the driver has gone inactive before the driver is turned off. Instructions executed by the microprocessor permit specification of portions of the internal registers as sources and destinations and specification of the size of an ALU operation, permitting easy operation on data ranging from bytes through 24-bit pointers. Instructions are executed in an instruction pipeline and a separate I/O instruction pipeline. Some pipeline stalls are avoided by means of a special MOVE instruction which differs from an ordinary MOVE instruction in that it does not cause pipeline stall when it reads data from a register loaded by a preceding READ instruction. The microprocessor also has an Intel/Motorola pin whose input specifies the type of host processor the coprocessor is working with and further executes I/O instructions which permit the same code to be used with either host processor.

Claims

1. In a processor able to share memory containing data with another processor and having instruction execution means for executing instructions, the improvement comprising:

data format signal receiving means for receiving a data format signal from a source external to the processor which provides the data format signal independently of the instructions currently being executed and the data currently being processed by the processor, the data format signal indicating a data format which is an order of pluralities of bytes in the memory employed by the other processor; and

operation means in the instruction execution means, the operation means being responsive to data format dependency indicating means in certain ones of the instructions which indicate that the manner in which a read or write operation specified by the instruction is executed depends on the data format employed by the other processor and being also responsive to the data format signal to perform the operation specified by the instruction as required by the data format indicated by the data format signal.

2. The processor set forth in claim 1 wherein:

the number of bytes in the pluralities of bytes is two;

a first one of the other processors is able to place the two bytes in a first order in the memory;

a second one of the other processors is able to place the two bytes in a second order in the memory;

the data format signal indicates either the first order or the second order; and

the read operation places any two bytes being read from the memory in the first order when the data format signal indicates the second order and the write operation places any two bytes being written to the memory in the second order when the data format signal indicates the second order.

3. The processor set forth in claim 2 wherein:

the first order is that employed by processors of the 680×

0 type; and

the second order is that employed by processors of the 80×

86 type.

4. A data processing system comprising:

a memory for storing dam;

a first processor which is coupled to the memory and processes the data, the first processor belonging to one of a plurality of processor types, each processor type employing a different data format which defines an order of pluralities of bytes in the memory for certain items of the data; and

a second processor which is coupled to the memory and processes the data, the second processor executing instructions which specify operations and which include at least one instruction which specifies a read or a write operation and has data format dependency indicating means which indicate that the manner in which the processor performs the operation specified by the instruction is dependent on the data format employed by the first processor for the certain items and the second processor including

data format signal receiving means for receiving a data format signal from a source external to the second processor which provides the data format signal independently of the instructions currently being executed and the data currently being processed by the second processor, the data format signal indicating the data format employed by the first processor, and

operation means responsive to the data format signal and the data format dependency indicating means for performing the operation specified by the instruction as required by the data format indicated by the data format signal.

5. The system set forth in claim 4 wherein:

the number of bytes in the pluralities of bytes is two;

a first one of the types of processors is able to place he two bytes in a first order in the memory;

a second one of the types of processors is able to place the two bytes in a second order in the memory;

the data format signal indicates either the first order or the second order; and

the read operation places any two bytes read from the memory in the first order when the data format signal indicates the second order and the write operation places any two bytes written to the memory in the second order when the data format signal indicates the second order.

6. The system set forth in claim 5 wherein:

the first one of the types is the 680×

0 type; and

the second one of the types is the 80×

86 type.