Mass simultaneous sealing and electrical connection of electronic devices

• US 5,448,014 A
• Filed: 01/27/1993
• Issued: 09/05/1995
• Est. Priority Date: 01/27/1993
• Status: Expired due to Term

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: TRW Limited (Zeppelin - Stiftung der Stadt Friedrichshafen)
• Inventors: Kong, Alvin M., Chan, Steven S., Lau, James C.
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): Horgan, Christopher
• Application Number:
  US08/009,530
• Time in Patent Office: 951 Days
• Field of Search: 174/52.3, 174/52.2, 174/51, 174/52.1, 174/52.4, 174/52.5, 29/832, 29/825, 29/830, 29/860, 257/678, 257/704, 257/774
• US Class Current: 174/539
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H03H 9/059 consisting of mounting pads or bumps
• CPC Class Codes: H03H 9/1071 the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the SAW device
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

The present invention provides a new and effective method for the sealing and electrical testing of electronic devices; and particularly for surface acoustic wave devices. In accordance with the present invention, the cost and size of making hermetically sealed packages for electronic devices and of electrically testing each device is significantly reduced over the prior art by making use of mass simultaneous sealing and electrical connection at the wafer level, and by using substrates with hermetically sealed and electrically conductive via holes. Further, cost reduction is effected by making use of final electrical testing with wafer probe test techniques before dicing.

Claims

1. A method of mass sealing and testing electronic devices, comprising the steps of:

(a) initially aligning a cover wafer having a plurality of electrically conductive elements therein over a plurality of individual electronic devices supported at a single substrate

(b) next both;

(i) sealing each electronic device by bonding the aligned cover wafer against the substrate wafer; and

,

(ii) forming an electrical communication between the electrically conductive elements in the cover wafer and the electronic devices supported at the substrate wafer; and

,

(c) finally testing the plurality of sealed electronic devices;

wherein steps (b)(i) and (b)(ii) both take place while at the wafer level.

2. The method of claim 1 further comprising a step, subsequent to step (c), of dicing the wafer-level bonded wafers into a plurality of individual sealed packages each containing a tested electronic device.

3. The method of claim 1 wherein step (c) includes a wafer probe electrical testing technique.

4. The method of claim 1 wherein the cover wafer comprises an electrically nonconductive material having thermal expansion characteristics similar to the thermal expansion characteristics of the substrate wafer.

5. The method of claim 4 wherein the substrate wafer is quartz and the cover wafer is glass-ceramic.

6. The method of claim 4 wherein sealing step (b)(i) results in the formation of a hermetic seal about each of the electronic devices.

7. The method of claim 6 wherein the plurality of electrically conductive elements in the cover wafer comprise hermetically sealed conductive vias which are adapted to connect the electronic devices to external electrical terminals.

8. The method of claim 1 wherein the sealing step (b)(i) is carried out at a relatively low temperature and during which step the cover wafer is attached to the substrate wafer by a grid of solder strips patterned about each electrical device;

wherein patterning of the grid is carried out prior to the sealing step (b)(i); and

wherein said relatively low temperature is less than 200 degrees Celsius.

9. The method of claim 8 wherein the grid of solder strips maintains a separation between the substrate wafer and the cover wafer.

10. The method of claim 8 wherein the sealing step (b) (i) results in the formation of a hermetic solid liquid interdiffusion bond.

11. The method of claim 10 wherein the hermetic solid liquid interdiffusion bond is formed between a gold grid patterned upon one of the wafers and an indium grid patterned upon the other of the two wafers;

wherein patterning of the grids is carried out prior to the sealing step (b)(i).

12. The method of claim 8 wherein the recited dicing step comprises dicing the bonded and tested wafers down center lines of the grid of solder strips.

13. The method of claim 12 wherein the seal formed by the sealing step (b)(i) is a hermetic seal.

14. The method of claim 13 wherein the electronic devices are surface acoustic wave devices.

19. The method of claim 1 further comprising a step prior to step (c) of forming a solder layer on an outer side of one of said wafers for subsequent use in solder attachment procedures.

20. The method of claim 9 further comprising a multiple layer grid, wherein said solder strips comprise at least one layer of said grid;

and wherein said multiple layer grid additionally includes a barrier layer, wherein said barrier layer at least in part aids in maintaining the separation between the substrate wafer and the cover wafer.

21. The method of claim 1 wherein the steps (b)(i) and (b)(ii) both take place essentially concurrently.

15. A wafer level package comprising:

a single substrate wafer and a plurality of individual electronic devices, wherein said electronic devices are supported by said substrate wafer at the wafer level;

a cover wafer bonded against said substrate wafer over said electronic devices;

a grid of bonding material patterned upon said substrate wafer in a manner separating each one of said electronic devices supported thereby from the remaining of said electronic devices supported thereby;

wherein said bonding material and said cover wafer aid in forming a seal for substantially each cue of said electronic devices at the wafer level;

a plurality of electrically conductive elements in said cover wafer, wherein said electrically conductive elements are in electrical communication with said electronic devices at the wafer level.

16. The wafer level package of claim 15 wherein each of said substrate wafer and said cover wafer are at least one inch wide.

17. The wafer level package of claim 15 wherein the seal is a hermetic seal;

and wherein the cover wafer comprises an electrically nonconductive material having thermal expansion characteristics similar to the thermal expansion characteristics of the substrate wafer; and

wherein the plurality of electrically conductive elements in the cover wafer comprise hermetically sealed conductive vias.

18. The wafer level package of claim 17 wherein the electronic devices are surface acoustic wave devices.

22. The wafer level package of claim 15 wherein the electronic devices are surface acoustic wave devices.