Multiprocessing apparatus

• US 5,448,470 A
• Filed: 09/08/1992
• Issued: 09/05/1995
• Est. Priority Date: 09/05/1991
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Itou, Atsushi, Tsubone, Tsunehiko, Tamura, Naoyuki, Kato, Shigekazu, Nishihata, Kouji
• Primary Examiner(s): Envall, Jr., Roy N.
• Assistant Examiner(s): BROWN, THOMAS
• Application Number:
  US07/941,905
• Time in Patent Office: 1,092 Days
• Field of Search: 364/131-137, 364/468, 364/469, 364/478, 364/474.11, 364/DIG. 1, 364/138
• US Class Current: 700/2
• CPC Class Codes: G05B 19/4184 characterised by fault tolerance, reliability of production system
• CPC Class Codes: G05B 19/41845 characterised by system universality, reconfigurability, modularity
• CPC Class Codes: G05B 2219/31361 Verify if right controllers are connected to carrier, conveyor controller
• CPC Class Codes: G05B 2219/31362 Verify correct configuration of system
• CPC Class Codes: G05B 2219/35291 Record history, log, journal, audit of machine operation
• CPC Class Codes: G05B 2219/45026 Circuit board, pcb
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
• CPC Class Codes: Y10S 414/135 Associated with semiconductor wafer handling
• CPC Class Codes: Y10S 414/139 including wafer charging or discharging means for vacuum chamber
• CPC Class Codes: Y10S 414/14 Wafer cassette transporting

Abstract

A multiprocessing apparatus has a plurality of process processors connected to a carrier processor and controlled by a control system, wherein there are provided connection information signal generating means for generating a connection information signal expressing information of connection of the plurality of process processors to the carrier processor; switching means for generating a registration information signal expressing information of registration of connection of the plurality of process processors to the carrier processor; and control means for carrying out a control process while logically judging a matching state between the connected process processors and the registered process processors by reference to the connection information and the registration information. Thus, it is possible to provide a multiprocessing apparatus in which the number of process processors to be connected to the carrier processor can be securely increased or decreased.

Claims

1. A wafer vacuum processing apparatus, comprising:

a carrier processor for carrying a wafer under a vacuum;

a plurality of wafer process processors connected to said carrier processor for processing said wafer under the vacuum, respectively;

a plurality of process controllers for respectively controlling said wafer process processors,

wherein each of said process controllers includes means for generating a connection information signal for expressing that each of said wafer process processors is directly connected to said carrier processor respectively; and

a carrier controller for controlling said carrier processor and said process controllers,

wherein said carrier controller includes;

switching means for generating a registration information signal expressing registration of connection of said wafer process processor to said carrier processor,

control means for carrying out a control process while logically judging a matching state between the respective wafer process processors and the registered wafer process processor by referencing the connection information signal and the registration information signal, and

display means for displaying guidance based on the matching state due to said control means.

2. A wafer vacuum processing apparatus according to claim 1, further comprising:

failure history information storage means for storing information of the history of failures occurring in said wafer vacuum processing apparatus,

wherein said control means executes a process of controlling the connected wafer process processors by reference to the failure history information.

3. A wafer vacuum processing apparatus according to claim 1, further comprising:

a processor state information storage means for storing information of the states of the respective wafer process processors,

wherein said control means executes a process of controlling the connected wafer process processors by references to the processor state information.

4. A wafer vacuum processing apparatus according to claim 1, wherein said wafer process controllers and said carrier controller respectively include processor connection information storage means, and said control means controls said processor connection information storage means to store information expressing connection relationships between said process processors.

5. A method of controlling a wafer vacuum processing apparatus which includes a carrier processor for carrying a wafer under a vacuum, a plurality of wafer process processors connected to said carrier processor for respectively processing said wafer under said vacuum, a plurality of process controllers for respectively controlling said wafer process controllers, and a carrier controller for controlling said carrier processor and said process controllers, said method comprising the steps of:

generating a connection information signal for expressing information of respective direct connection of said plurality of wafer process processors to said carrier processor;

generating a registration information signal expressing information of registration of connection of said plurality of wafer process processors to said carrier processor;

logically judging a matching state between the connected wafer process processors and the registered wafer process processors respectively, by referencing the generated connection information signal and the registration information signal; and

displaying guidance based on the matching state due to the logical judgement.