Memory stack with an integrated interconnect and mounting structure

• US 5,448,511 A
• Filed: 06/01/1994
• Issued: 09/05/1995
• Est. Priority Date: 06/01/1994
• Status: Expired due to Fees

• Current Assignee: Storage Technology Corp (Oracle Corporation)
• Original Assignee: Storage Technology Corp (Oracle Corporation)
• Inventors: Paurus, Floyd G., Szerlip, Stanley R.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): MAI, SON LUU
• Application Number:
  US08/252,609
• Time in Patent Office: 461 Days
• Field of Search: 365/52, 365/53, 365/63, 361/749, 361/750, 361/751, 257/686, 257/684, 257/685, 257/777, 439/77, 439/67
• US Class Current: 365/52
• CPC Class Codes: H01L 2225/06579 TAB carriers; beam leads
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H05K 1/189 characterised by the use of a flexible or folded printed circuit H05K3/326 takes precedence

Abstract

A memory stack includes a flexible interconnect device having a plurality of rigid sections connected together by a plurality of flexible sections. Memory devices such as dice or chips are mounted on the flexible interconnect structure and the structure is folded to at the flexible sections to form a stack. Connections among memory device I/Os and interconnect device mounting contacts are made via traces in a signal layer. A thermal conduction layer can be added to increase heat conduction away from the memory devices.

Claims

1. A memory stack, comprising:

(a) an interconnect device, comprising

i. a plurality of rigid sections,

ii. a plurality of flexible sections connected between said rigid sections,

iii. a plurality of mounting contacts on each of said rigid sections, and

iv. a plurality of traces electrically connected to said mounting contacts; and

(b) a plurality of memory devices, each memory device being mounted on one of said rigid sections of said interconnect device, wherein I/O contacts of said memory devices are electrically connected to said traces of said interconnect device,

wherein said interconnect device is folded at said flexible sections to form a stack of memory devices.

2. The memory stack of claim 1, wherein said interconnect device further comprises second I/O contacts electrically connected to said traces, wherein said I/O contacts of said memory devices are electrically connected to said traces via said second I/O contacts.

3. The memory stack of claim 1, further comprising an enclosure mounted on each of said rigid sections to cover each of said memory devices.

4. The memory stack of claim 1, further comprising a decoupling capacitor mounted on one of said rigid sections.

5. The memory stack of claim 1, further comprising a decoupling capacitive element integrated into said interconnect device.

6. The memory stack of claim 1, wherein said interconnect device further comprises a thermal conduction layer.

7. The memory stack of claim 6, further comprising a heat sink coupled to said thermal conduction layer.

8. The memory stack of claim 1, wherein said memory devices are mounted on a single side of said interconnect device.

9. The memory stack of claim 1, wherein said memory devices are mounted on both sides of said interconnect device.

10. The memory stack of claim 1, further comprising a thermal plane interposed between folds of said interconnect device.

11. The memory stack of claim 1, further comprising a thermal plane interposed between adjacent memory devices in said memory stack.

12. The memory stack of claim 1, further comprising an interconnect extension extending from the end of said interconnect device at the top of the memory stack.

13. The memory stack of claim 1, wherein said mounting contacts are positioned on a bottom surface of said interconnect device.

14. The memory stack of claim 13, wherein said mounting contacts are further positioned on an end section of said interconnect device.

15. A memory stack, comprising:

(a) a flexible interconnect device, comprising

i. a plurality of mounting contacts on said flexible interconnect device,

ii. a plurality of traces connected to said mounting contacts and forming a first layer of said flexible interconnect device, and

iii. thermal conduction means for conducting heat, said thermal conduction means forming a second layer of said flexible interconnect device; and

(b) a plurality of memory devices, each memory device being mounted on said flexible interconnect device, wherein I/O contacts of said memory devices are electrically connected to said traces of said flexible interconnect device, wherein said flexible interconnect device is folded to form a stack of memory devices.

16. The memory stack of claim 15, wherein said flexible interconnect device further comprises second I/O contacts electrically connected to said traces, wherein said I/O contacts of said memory devices are electrically connected to said traces via said second I/O contacts.

17. The memory stack of claim 15, further comprising an enclosure mounted on said flexible interconnect device and covering said memory device.

18. The memory stack of claim 15, further comprising a decoupling capacitive element integrated into said flexible interconnect device.

19. The memory stack of claim 15, further comprising a heat sink coupled to said thermal conduction means.

20. The memory stack of claim 15, wherein said memory devices are mounted on a single side of said flexible interconnect device.

21. The memory stack of claim 15, wherein said memory devices are mounted on both sides of said flexible interconnect device.

22. The memory stack of claim 15, further comprising a thermal plane interposed between folds of said flexible interconnect device.

23. The memory stack of claim 15, further comprising a thermal plane interposed between adjacent memory devices in said memory stack.

24. The memory stack of claim 15, further comprising an interconnect extension extending from the end of said flexible interconnect device at the top of the memory stack.

25. The memory stack of claim 15, wherein said mounting contacts are positioned on a bottom surface of said flexible interconnect device.

26. The memory stack of claim 25, wherein said mounting contacts are further positioned on an end section of said flexible interconnect device.

31. The memory stack of claim 15, wherein said first layer is interposed between said second layer and said plurality of memory devices.

32. The memory stack of claim 15, wherein said second layer is interposed between said first layer and said plurality of memory devices.

27. A circuit board having a memory stack, wherein said memory stack comprises:

(a) a flexible interconnect device, comprising

i. a plurality of mounting contacts on said flexible interconnect device,

ii. a plurality of traces connected to said mounting contacts and forming a first layer of said flexible interconnect device, and

iii. thermal conduction means for conducting heat, said thermal conduction means forming a second layer of said flexible interconnect device; and

(b) a plurality of memory devices having I/O contacts and mounted on said flexible interconnect device, wherein said I/O contacts of said memory devices are electrically connected to said traces of said flexible interconnect device;

wherein said flexible interconnect device is folded to form a stack of memory devices.

28. The memory stack of claim 27, wherein said flexible interconnect device further comprises second I/O contacts electrically connected to said traces, wherein said I/O contacts of said memory devices are electrically connected to said traces via said second I/O contacts.

29. The memory stack of claim 27, further comprising a decoupling capacitive element integrated into said flexible interconnect device.

33. The memory stack of claim 27, wherein said first layer is interposed between said second layer and said plurality of memory devices.

34. The memory stack of claim 27, wherein said second layer is interposed between said first layer and said plurality of memory devices.

30. A method of manufacturing a memory stack, comprising the steps of:

(a) mounting a plurality of memory devices on a flexible interconnect structure; and

(b) folding said flexible interconnect structure so that said memory devices are positioned in a stack

wherein said flexible interconnect structure includes

i. a plurality of rigid sections,

ii. a plurality of flexible sections connected between said rigid sections,

iii. a plurality of mounting contacts on each of said rigid sections, and

iv. a plurality of traces electrically connected to said mounting contacts.