Semiconductor device for logical operation processing and method of operation processing therefor

• US 5,448,713 A
• Filed: 03/28/1994
• Issued: 09/05/1995
• Est. Priority Date: 01/29/1990
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Hamamoto, Takeshi
• Primary Examiner(s): Downs, Robert W.
• Assistant Examiner(s): Dorvil, Richemond
• Application Number:
  US08/218,958
• Time in Patent Office: 526 Days
• Field of Search: 395/3, 395/900, 395/21, 395/61, 395/425, 395/400, 364/715.01, 364/715.06, 364/DIG. 1, 365/49
• US Class Current: 711/154
• CPC Class Codes: G06N 7/04 Physical realisation
• CPC Class Codes: Y10S 706/90 Fuzzy logic
• CPC Class Codes: Y10S 706/919 Designing, planning, programming, CAD, CASE

Abstract

A device for executing fuzzy inference includes a first storage area constituting a condition portion of a fuzzy set and a second storage area constituting a conclusion portion of the fuzzy set. The first storage area stores membership functions of the condition portion in order to develop a first bit mapping while the second storage area stores membership functions of the conclusion portion in order to develop a second bit mapping. Each of the first and second storage areas has X addresses which are designated by an input signal and Y addresses which are designated by a membership value. The device further includes circuitry for detecting corresponding rows of the first and second storage areas on which signal potentials are both a logical true after application of input signals to the first and second storage areas, other circuitry for detecting a Y address specifying a highest-order row among the detected rows, and additional circuitry for deriving a membership value in accordance with the detected Y address. The first and second storage areas preferably each include an array of content addressable memory cells having X addresses applied by an input pattern. A row detecting circuit detects coincidence/non-coincidence of signal potentials on coincidence detection lines of the content addressable memory cell arrays. The construction realizes a device for executing fuzzy inference which is not limited by the number of rules or inputs and executes MIN-MAX operations at a high speed.

Claims

1. A semiconductor device for an operation processing, comprising:

a first storage area including a plurality of first memory cells disposed in rows and columns for storing first data in a first bit mapping, said first data representing a first relationship between a first input signal and a first output signal, said first storage area receiving the first input signal as a column designating signal and generating the first output signal as a row designating signal, said plurality of first memory cells transferring signal potentials according to storage data onto associated rows in response to the first input signal;

a second storage area including a plurality of second memory cells disposed in rows and columns for storing second data in a second bit mapping, said second data representing a second relationship between a second input signal and a second output signal, said second storage area receiving the second input signal as a column designating signal and generating the second output signal as a row designating signal, said plurality of second memory cells transferring signal potentials according to storage data onto associated rows in response to the second input signal; and

means responsive to signal potentials on individual rows of said first and second storage area for determining a relationship in magnitude between the first and second output signals.

2. A semiconductor device according to claim 1, wherein the rows of said first and second storage areas have a one-to-one correspondence relationship, and said means for determining includes a plurality of detecting means each receiving signal potentials on corresponding ones of the rows of said first storage area and said second storage area to detect coincidence or non-coincidence of the signal potentials on the corresponding rows, highest-order row detecting means responsive to outputs of said plurality of detecting means for detecting a highest-order one of the rows which exhibit coincidence and outputting a row address indicative of the highest-order row thus detected, and means responsive to the row address from said highest-order row detecting means for deriving a signal indicative of a value of a smaller one of the first and second output signals.

3. A semiconductor device according to claim 1, wherein the rows of said first storage area and the rows of said second storage area have a one-to-one correspondence relationship, and said determining means includes a plurality of detectors each receiving signal potentials on corresponding ones of the rows of said first storage and said second storage area to detect coincidence or non-coincidence of the signal potentials on the corresponding rows, highest-order row detecting means responsive to outputs of said plurality of detectors for detecting a highest-order one of the rows which exhibit coincidence, and highest-order row decoding means responsive to an output of said highest-order row detecting means for outputting an address indicative of the thus detected highest-order row in the form of a binary notation.

4. A semiconductor device according to claim 3, wherein said coincidence/non-coincidence detecting means includes a plurality of logical product gates.

5. A semiconductor device according to claim 4, wherein said highest-order row detecting means includes a plurality of first logical gates each having a false input and a true input for making a logical product operation on signals received at said false and true inputs, said first logical gates being provided corresponding to said logical product gates of said coincidence/non-coincidence detecting means, each of said first logical gates being connected in such a manner as to receive at said false input thereof an output of a corresponding one of said logical product gates and receive at said true input thereof an output of an adjacent one to said corresponding first logical gate on a higher order side, one of said first logical gates which receives outputs of logical product gates associated with the highest-order rows in said first and second storage areas receiving at said true input thereof a signal fixed to the logical true, and a plurality of second logical gates provided corresponding to said logical product gates except one associated with the highest-order positions in said first and second storage areas, each of said second logical gates being connected in such a manner as to receive at one input thereof an output of a corresponding one of said logical product gates and receive at the other input thereof an output of an adjacent one of said first logical gates on the higher order side to make a logical product operation on the received signals and output a resultant signal.

6. A semiconductor device according to claim 5, wherein said highest-order row decoding means includes a plurality of transistor trains corresponding to said second logical gates, each of said transistor trains being connected so as to provide, when the output of a corresponding one of said second logical gates represents the logical true, a binary notation of an address indicative of a corresponding row.

7. A semiconductor device according to claim 1, wherein said semiconductor device is a device for executing a fuzzy operation, and the first output signal provides a membership value for the first input signal to construct a fuzzy set of a condition portion while the second output signal provides a membership value for the second input signal to construct a fuzzy set of a conclusion portion.

8. A semiconductor device according to claim 7, wherein said first storage area constituting the condition portion and said second storage area constituting the conclusion portion are separate storage arrays.

9. A semiconductor device according to claim 7, wherein said first storage area constituting the condition portion and said second storage area constituting the conclusion portion are formed in a common storage array, and said first storage area and said second storage area are disposed in an alternate relationship in said common storage array.

10. A semiconductor device according to claim 7, wherein the fuzzy operation includes a plurality of rules, and membership values of the plurality of rules are disposed in a predetermined order in each of said first and second storage areas.

11. A semiconductor device according to claim 7, wherein the first input signal includes a plurality of kind of input data, and membership values for each of the plurality of kinds of input data area arranged cyclically in an order in each of said first and second storage areas.

12. An operation method in a semiconductor device which includes a first storage area for storing first data in a first bit mapping, said first data representing a first relationship between a first input signal and a first output signal, and a second storage area for storing second data in a second bit mapping, said second data representing a second relationship between a second input signal and a second output signal, each of said first and second storage area including a plurality of memory cells disposed in columns and rows, the rows of said first storage area having a one-to-one correspondence relationship to the rows of said second storage area, comprising the steps of:

selecting a column from said first storage area using the first input signal as a column designating signal and reading out data of those of said memory cells connected to the thus selected column on individual rows;

selecting a column from said second storage area using the second input signal as a column designating signal and reading out data of those of said memory cells connected to the thus selected column on individual rows;

comparing the data read out on the individual rows of said first storage area with the data read out on corresponding rows of said second storage area to detect coincidence;

detecting a highest-order row among the rows for which coincidence has been determined at the preceding comparing step; and

specifying the thus detected highest-order row to determine a relationship in magnitude between the first and second output signals and deriving a signal indicative of one of the first and second output signals in accordance with a result of such determination.