Integrated circuit microprocessor with programmable chip select logic
First Claim
1. An integrated circuit microprocessor comprising:
- a central processing unit;
bus controller means coupled to the central processing unit and to a plurality of pins of the integrated circuit microprocessor for operating a bus external to the integrated circuit microprocessor; and
chip select means coupled to the central processing unit and to a pin of the integrated circuit microprocessor for selectively providing, under control of the central processing unit, a chip select signal to a device external to the microprocessor;
wherein the improvement comprises;
a chip select control register means coupled to the chip select means and to the central processing unit for storing, under control of the central processing unit, a first bit field; and
the chip select means is responsive to the states of the bits of the first bit field of the chip select control register means to selectively assert the chip select signal only while the bus controller means is executing a write cycle of the bus, only while the bus controller is executing a read cycle of the bus or while the bus controller is executing either a read cycle or a write cycle of the bus.
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Accused Products
Abstract
An integrated circuit microprocessor has on-board programmable chip select logic. Each of several chip select outputs is individually programmable by means of one or more control register bit fields. For instance, each chip select is asserted for bus cycles within an address range whose starting address and block size are both programmable. In addition, each chip select can be programmed to be active on read cycles only, on write cycles only, or on both read and write cycles. Each chip select can be programmed to be active during interrupt acknowledge cycles only if the interrupt being acknowledged has the same priority level as has been programmed for that chip select. In addition, the timing of the assertion of each chip select is programmable to coincide with either the address strobe or data strobe of the bus cycle. The chip select logic is designed so that it is configured to come out of reset by producing an active chip select signal during the first bus cycle run by the processor following the reset. This chip select is appropriate for selecting a boot ROM, and may later be re-programmed for other use. The chip select logic is capable of supporting cycle-by-cycle dynamic bus sizing by asserting appropriate cycle termination signals. The chip select logic can also insert a programmable number of wait states into a bus cycle to accommodate slow peripherals or can cause a fast termination of a bus cycle to improve the utilization of fast peripherals.
68 Citations
36 Claims
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1. An integrated circuit microprocessor comprising:
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a central processing unit; bus controller means coupled to the central processing unit and to a plurality of pins of the integrated circuit microprocessor for operating a bus external to the integrated circuit microprocessor; and chip select means coupled to the central processing unit and to a pin of the integrated circuit microprocessor for selectively providing, under control of the central processing unit, a chip select signal to a device external to the microprocessor; wherein the improvement comprises; a chip select control register means coupled to the chip select means and to the central processing unit for storing, under control of the central processing unit, a first bit field; and the chip select means is responsive to the states of the bits of the first bit field of the chip select control register means to selectively assert the chip select signal only while the bus controller means is executing a write cycle of the bus, only while the bus controller is executing a read cycle of the bus or while the bus controller is executing either a read cycle or a write cycle of the bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An integrated circuit microprocessor comprising:
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a central processing unit; bus controller means coupled to the central processing unit and to a plurality of pins of the integrated circuit microprocessor for operating a bus external to the integrated circuit microprocessor; and chip select means coupled to the central processing unit and to a pin of the integrated circuit microprocessor for selectively providing, under control of the central processing unit, a chip select signal to a device external to the microprocessor; wherein the improvement comprises; a chip select control register means coupled to the chip select means and to the central processing unit for storing, under control of the central processing unit, a first bit field; and the chip select means is responsive to the states of the bits of the first bit field of the chip select control register means to selectively assert the chip select signal synchronized with a data strobe signal of the bus or synchronized with an address strobe signal of the bus. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A method of operating an integrated circuit microprocessor comprising a central processing unit, a bus controller and a chip select signal generator, the method comprising the steps of:
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storing, under control of the central processing unit, a first bit field in a chip select control register; and selectively asserting the chip select signal, in response to the states of the bits of the first bit field, only while the bus controller is executing a write cycle, only while the bus controller is executing a read cycle or while the bus controller is executing either a read cycle or a write cycle. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
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28. A method of operating an integrated circuit microprocessor comprising a central processing unit, a bus controller and a chip select signal generator, the method comprising the steps of:
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storing, under control of the central processing unit, a first bit field in a chip select control register; and selectively asserting the chip select signal, in response to the states of the bits of the first bit field, synchronized with a data strobe signal or synchronized with an address strobe signal. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36)
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Specification