Intermittent operation receiver
First Claim
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1. A receiver for receiving a desired signal which is intermittently transmitted for said receiver, said receiver comprising:
- an amplifier for amplifying a radio frequency (RF) signal which is obtained by an antenna, said RF signal comprising a sync signal followed by an address signal specifying the receiver;
frequency converting means for converting said RF signal into two low frequency (LF) signals which have different signal phases;
a demodulator for demodulating said two LF signals to obtain a data signal;
timing control means for detecting from said data signal said sync signal and said address signal and for generating at least a first control signal which rises earlier than a time interval of said desired signal and which holds for at least said time interval, a second control signal which rises a predetermined time later than said first control signal and earlier than said time interval and which falls earlier than said time interval, and a third control signal which rises earlier than said second control signal and partially overlaps with said second control signal, in synchronization with said sync signal and said address signal;
means for energizing at least one part of the receiver in response to said first control signal;
a level detector for detecting a level of at least one of said LF signals before said time interval in response to said second control signal, said detected signal level being larger than a first predetermined level;
a comparator for generating an output voltage when said detected signal level is larger than a second predetermined level;
a memory for holding the output voltage of said comparator for at least said time interval, said memory being reset in response to said third control signal; and
level control means for controlling levels of said LF signals in accordance with said detected signal level.
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Abstract
A direct conversion type FSK receiver has an intermittent reception mode and includes a detecting and holding device in a low frequency unit and a gain control device in a high frequency unit. The receiver starts a reception operation in response to an intermittent reception control signal and controls the gain of the high frequency unit based on the detection of the received signal strength level before an interval of time during which the receiver receives a signal transmitted for the receiver and maintains the controlled gain for that interval of time. As a result, the receiver has reduced reception disturbance, which disturbance is due to intermodulation occurring when a large input signal is received.
36 Citations
1 Claim
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1. A receiver for receiving a desired signal which is intermittently transmitted for said receiver, said receiver comprising:
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an amplifier for amplifying a radio frequency (RF) signal which is obtained by an antenna, said RF signal comprising a sync signal followed by an address signal specifying the receiver; frequency converting means for converting said RF signal into two low frequency (LF) signals which have different signal phases; a demodulator for demodulating said two LF signals to obtain a data signal; timing control means for detecting from said data signal said sync signal and said address signal and for generating at least a first control signal which rises earlier than a time interval of said desired signal and which holds for at least said time interval, a second control signal which rises a predetermined time later than said first control signal and earlier than said time interval and which falls earlier than said time interval, and a third control signal which rises earlier than said second control signal and partially overlaps with said second control signal, in synchronization with said sync signal and said address signal; means for energizing at least one part of the receiver in response to said first control signal; a level detector for detecting a level of at least one of said LF signals before said time interval in response to said second control signal, said detected signal level being larger than a first predetermined level; a comparator for generating an output voltage when said detected signal level is larger than a second predetermined level; a memory for holding the output voltage of said comparator for at least said time interval, said memory being reset in response to said third control signal; and level control means for controlling levels of said LF signals in accordance with said detected signal level.
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Specification
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Current AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
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Original AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
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InventorsImagawa, Yasumi, Yokozaki, Katsushi
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Primary Examiner(s)Urban, Edward F.
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Assistant Examiner(s)SOBUTKA, PHILIP
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Application NumberUS08/229,109Time in Patent Office505 DaysField of Search455/343, 455/38, 455/38.2, 455/38.3, 455/228, 455/234.1, 455/249.1, 375/98, 370/95.3, 370/95.1, 340/825.44, 340/825.57US Class Current455/343.5CPC Class CodesH03G 3/3068 Circuits generating control...
