Precharging output driver circuit

• US 5,450,019 A
• Filed: 01/26/1994
• Issued: 09/12/1995
• Est. Priority Date: 12/17/1991
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: McClure, David C., Lysinger, Mark A., Slemmer, William C.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): Sanders, Andrew
• Application Number:
  US08/185,650
• Time in Patent Office: 594 Days
• Field of Search: 307/451-452, 307/481, 307/943, 307/475, 307/296.5, 307/296.8, 365/203
• US Class Current: 326/28
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits

Abstract

A push-pull output driver circuit is disclosed which includes control circuitry for controlling the gates of the driver transistors to effect precharge of the output terminal at the beginning of a cycle. Precharge is initiated at the beginning of each cycle, for example indicated by an address transition. The prior data state at the output is stored, and enables the opposing driver transistor from that which drove the stored prior data state by enabling a gated level detector with hysteresis, such as a Schmitt trigger, associated therewith. The transistor that drove the stored prior data state is disabled, thus precluding oscillations during precharge. The gated Schmitt triggers each receive the voltage of the output terminal and, when enabled, turn on a transistor which couples the output terminal to the gate of the driver transistor. The Schmitt triggers also control the precharge to terminate when the output terminal has reached an intermediate voltage, and so that oscillations are minimized as a result of the hysteresis characteristic. Connection of the output terminal to the gate of the precharging driver transistor helps to eliminate overshoot during precharge.

Claims

1. An output driver for an integrated circuit, comprising:

a first driver transistor, having a conduction path connected between a first bias voltage and an output terminal, and having a control terminal;

a memory for storing a data state corresponding to the voltage at said output terminal, said memory having an input coupled to said output terminal;

a first driver control circuit, having a data input, having a control input for receiving a precharge signal, having an input coupled to the output of said memory, and having an output coupled to the control terminal of said first driver transistor, said first driver control circuit;

for turning off said first driver transistor responsive to said precharge signal in combination with the contents of said memory being at a first data state having a logic level corresponding to said first bias voltage;

for turning on said first driver transistor responsive to said precharge signal in combination with the contents of said memory being at a second data state having a logic level corresponding to a second bias voltage; and

for turning on said first driver transistor responsive to the absence of said precharge signal in combination with receiving said first logic state at its data input.

2. The output driver of claim 1, wherein said memory comprises:

a latch, having a data input coupled to said output terminal, and having a control input for receiving said precharge signal so that a data state corresponding to the voltage at said output terminal is latched into said latch responsive to said precharge signal.

3. The output driver of claim 1, wherein said first driver control circuit comprises:

a gated level detector, having an input coupled to the output terminal, and having an enable input coupled to said memory so as to be enabled responsive to the contents of said memory being at said second data state;

a logic circuit, having an input for receiving said precharge signal, and coupled to said gated level detector, for turning on said first driver transistor responsive to said gated level detector indicating, when enabled, that said output terminal is at a voltage substantially different from said first bias voltage.

4. The output driver of claim 3, wherein said logic circuit comprises:

a pass transistor having a conduction path coupled between said output terminal and the gate of said first driver transistor, and having its control terminal coupled to said gated level detector, so that said pass transistor is conductive responsive to said gated level detector indicating, when enabled, that said output terminal is at a voltage substantially different from said first bias voltage.

5. The output driver of claim 1, further comprising:

a second driver transistor, having a conduction path connected between said second bias voltage and said output terminal, and having a control terminal;

a second driver control circuit, having a data input, having a control input for receiving said precharge signal, having an input coupled to the output of said memory, and having an output coupled to the control terminal of said second driver transistor, said second driver control circuit;

for turning off said second driver transistor responsive to said precharge signal in combination with the contents of said memory being at said second data state;

for turning on said second driver transistor responsive to said precharge signal in combination with the contents of said memory being at said first data state; and

for turning on said second driver transistor responsive to the absence of said precharge signal in combination with receiving said second logic state at its data input.

6. The output driver of claim 5, wherein said first driver control circuit comprises:

a first gated level detector, having an input coupled to the output terminal, and having an enable input coupled to said memory so as to be enabled responsive to the contents of said memory being at said second data state; and

a first logic circuit, having an input for receiving said precharge signal, and coupled to said first gated level detector, for turning on said first driver transistor responsive to said first gated level detector indicating, when enabled, that said output terminal is at a voltage substantially different from said first bias voltage;

and wherein said second driver control circuit comprises;

a second gated level detector, having an input coupled to the output terminal, and having an enable input coupled to said memory so as to be enabled responsive to the contents of said memory being at said first data state;

a second logic circuit, having an input for receiving said precharge signal, and coupled to said second gated level detector, for turning on said second driver transistor responsive to said second gated level detector indicating, when enabled, that said output terminal is at a voltage substantially different from said second bias voltage.

7. An output driver circuit, comprising:

a pull-up transistor having a conduction path coupled between a power supply voltage and an output terminal, and having a control terminal;

a pull-down transistor having a conduction path coupled between a reference voltage and said output terminal, and having a control terminal;

a pull-up control circuit, having a data input for receiving a data signal, having an output coupled to the control terminal of said pull-up transistor, for controlling said pull-up transistor to drive said output terminal toward said power supply voltage responsive to said data signal at a first logic state;

a pull-down control circuit, having a data input for receiving a data signal, having an output coupled to the control terminal of said pull-down transistor, for controlling said pull-down transistor to drive said output terminal toward said reference voltage responsive to said data signal at a second logic state;

means for generating a precharge signal indicating the initiation of a new cycle;

means for storing, responsive to said precharge signal, the logic state at said output terminal;

a first level detector circuit, having an input coupled to said output terminal, having control inputs for receiving said precharge signal and for receiving the contents of said storing means so that said first level detector circuit is enabled responsive to said precharge signal in combination with said storing means storing said second logic state, and having an output coupled to said pull-up control circuit;

a second level detector circuit, having an input coupled to said output terminal, and having control inputs for receiving said precharge signal and for receiving the contents of said storing means so that said second level detector circuit is enabled responsive to said precharge signal in combination with said storing means storing said first logic state, and having an output coupled to said pull-down control circuit;

wherein said pull-up control circuit turns on said pull-up transistor responsive to said first level detector circuit indicating that the voltage at said output terminal is substantially different from the power supply voltage;

and wherein said pull-down control circuit turns on said pull-down transistor responsive to said second level detector circuit indicating that the voltage at said output terminal is substantially different from the reference voltage.

8. The output driver of claim 7, wherein said first and second level detector circuits each comprise a gated Schmitt trigger.

9. The output driver of claim 7, wherein said pull-up control circuit comprises:

a pass transistor, having a conduction path coupled between said output terminal and the control terminal of said pull-up transistor, and having a control terminal coupled to said first level detector circuit, so that said control terminal of said pull-up transistor is biased from said output terminal responsive to said first level detector circuit indicating that the voltage at said output terminal is substantially different from said power supply voltage.

10. The output driver of claim 9, wherein said pull-up transistor is a field effect transistor of a conductivity type such that it is turned off responsive to a voltage near said power supply voltage being applied to its gate.

11. The output driver of claim 10, wherein said pull-down control circuit comprises:

a pass transistor, having a conduction path coupled between said output terminal and the control terminal of said pull-down transistor, and having a control terminal coupled to said second trigger circuit, so that said control terminal of said pull-down transistor is biased from said output terminal responsive to said second trigger circuit indicating that the voltage at said output terminal is substantially different from said reference voltage;

wherein said pull-down transistor is a field effect transistor of a conductivity type such that it is turned off responsive to a voltage near said reference voltage being applied to its gate.

12. An integrated circuit, comprising:

functional circuitry for performing a data processing operation, said functional circuitry having an output;

an output terminal;

a first driver transistor, having a conduction path connected between a first bias voltage and said output terminal, and having a control terminal;

a memory for storing a data state corresponding to the voltage at said output terminal, said memory having an input coupled to said output terminal;

a first driver control circuit, having a data input coupled to the output of said functional circuitry, having a control input for receiving a precharge signal, having an input coupled to the output of said memory, and having an output coupled to the control terminal of said first driver transistor, said first driver control circuit;

for turning off said first driver transistor responsive to said precharge signal in combination with the contents of said memory being at a first data state having a logic level corresponding to said first bias voltage;

for turning on said first driver transistor responsive to said precharge signal in combination with the contents of said memory being at a second data state having a logic level corresponding to a second bias voltage; and

for turning on said first driver transistor responsive to the absence of said precharge signal in combination with receiving said first logic state from said functional circuitry.

13. The integrated circuit of claim 12, further comprising:

a second driver transistor, having a conduction path connected between said second bias voltage and said output terminal, and having a control terminal;

a second driver control circuit, having a data input coupled to the output of said functional circuitry, having a control input for receiving said precharge signal, having an input coupled to the output of said memory, and having an output coupled to the control terminal of said second driver transistor, said second driver control circuit;

for turning off said second driver transistor responsive to said precharge signal in combination with the contents of said memory being at said second data state;

for turning on said second driver transistor responsive to said precharge signal in combination with the contents of said memory being at said first data state; and

for turning on said second driver transistor responsive to the absence of said precharge signal in combination with receiving said second logic state from said functional circuitry.

14. The integrated circuit of claim 12, further comprising:

input circuitry coupled to said output terminal, for communicating an input signal received at said output terminal to said functional circuitry during write operations thereto.

15. A method of controlling a push-pull output driver for driving the output terminal of an integrated circuit, said push-pull output driver including a pull-up transistor connected between a power supply voltage corresponding to a first logic level and said output terminal, and including a pull-down transistor connected between a reference voltage corresponding to a second logic level and said output terminal, each of said pull-up and pull-down transistors having a control terminal, comprising the steps of:

responsive to an operating cycle of said integrated circuit indicating that the output terminal is to communicate a data state, driving said output terminal to a logic level by turning on the one of said pull-up and pull-down transistors corresponding to the data state to be communicated;

detecting the initiation of a new operating cycle of said integrated circuit;

responsive to said detecting step, turning off the one of said pull-up and pull-down transistors turned on in said driving step;

after the turning off step, turning on a pass transistor having a source-drain path coupled on one side to the output terminal and on another side to the control terminal of the one of said pull-up and pull-down transistors that is biased to drive the output terminal to the opposite logic level from that at the output terminal so as to couple the voltage at the output terminal to the control terminal of the one of said pull-up and pull-down transistors; and

responsive to said output terminal reaching a selected voltage between said power supply voltage and said reference voltage, turning off the one of said pull-up and pull-down transistors to which the voltage at the output terminal is coupled in the turning on step.

16. A method of controlling a push-pull output driver for driving the output terminal of an integrated circuit, said push-pull output driver including a pull-up transistor connected between a power supply voltage corresponding to a first logic level and said output terminal, and including a pull-down transistor connected between a reference voltage corresponding to a second logic level and said output terminal, each of said pull-up and pull-down transistors having a control terminal, comprising the steps of:

responsive to an operating cycle of said integrated circuit indicating that the output terminal is to communicate a data state, driving said output terminal to a logic level by turning on the one of said pull-up and pull-down transistors corresponding to the data state to be communicated;

detecting the initiation of a new operating cycle of said integrated circuit;

responsive to said detecting step, turning off the one of said pull-up and pull-down transistors turned on in said driving step;

after the turning off step, turning on the one of said pull-up and pull-down transistors that is biased to drive the output terminal to the opposite logic level from that previously driven at the output terminal;

responsive to said output terminal reaching a selected voltage between said power supply voltage and said reference voltage, turning off the one of said pull-up and pull-down transistors turned on in the turning on step;

detecting an output disable signal applied to said integrated circuit; and

responsive to said output disable signal, turning off both of said pull-up and pull-down transistors.

17. An output driver for an integrated circuit, comprising:

a first driver transistor, having a conduction path connected between a first bias voltage and an output terminal, and having a control terminal;

a first driver control circuit, having a data input, having a control input for receiving a precharge signal indicating precharge, having an input coupled to an output terminal, and having an output coupled to the control terminal of said first driver transistor, said first driver control circuit;

for turning off said first driver transistor during precharge responsive to the voltage at said output terminal being nearer said first bias voltage than a first off trip point;

for turning on said first driver transistor during precharge responsive to the voltage at said output terminal being nearer a second bias voltage than a first on trip point; and

when not in precharge, for turning on said first driver transistor responsive to receiving said first logic state at its data input;

a second driver transistor, having a conduction path connected between said second bias voltage and said output terminal, and having a control terminal;

a second driver control circuit, having a data input, having a control input for receiving said precharge signal, having an input coupled to the output terminal, and having an output coupled to the control terminal of said second driver transistor, said second driver control circuit;

for turning off said second driver transistor during precharge responsive to the voltage at said output terminal being nearer said second bias voltage than a second off trip point;

for turning on said second driver transistor during precharge responsive to the voltage at said output terminal being nearer said first bias voltage than a second on trip point; and

when not in precharge, for turning on said second driver transistor responsive to receiving said second logic state at its data input;

wherein said first on and second on trip points are at substantially different voltages from one another.

18. The output driver of claim 17, wherein said first on trip point is nearer said second bias voltage than said second on trip point, and said second on trip point is nearer said first bias voltage than said first on trip point.

19. The output driver of claim 18, wherein said first off trip point is nearer said first bias voltage than said first on trip point;

wherein said first driver control circuit is also for;

responsive to turning on said first driver transistor during precharge, maintaining said first driver transistor on until the voltage at said output terminal reaches said first off trip point;

wherein said second off trip point is nearer said second bias voltage than said second on trip point;

and wherein said second driver control circuit is also for;

responsive to turning on said second driver transistor during precharge, maintaining said second driver transistor on until the voltage at said output terminal reaches said second off trip point.

20. The output driver of claim 19, wherein said first and second driver control circuits each comprise a Schmitt trigger.

21. The output driver of claim 17, further comprising:

prior cycle data storing means, having a data input coupled to said output terminal, having an output, and having a control input for receiving said precharge signal so that a data state corresponding to the voltage at said output terminal is latched into said prior cycle data storing means responsive to said precharge signal;

wherein the output of said prior cycle storing means is coupled to said first and second driver control circuits in such a manner that said first driver control circuit is disabled responsive to the stored data state corresponding to said first bias voltage, and in such a manner that said second driver control circuit is disabled responsive to the stored data state corresponding to said second bias voltage.

22. A method of controlling a push-pull output driver for driving the output terminal of an integrated circuit, said push-pull output driver including a pull-up transistor connected between a power supply voltage corresponding to a first logic level and said output terminal, and including a pull-down transistor connected between a reference voltage corresponding to a second logic level and said output terminal, each of said pull-up and pull-down transistors having a control terminal, comprising the steps of:

responsive to an operating cycle of said integrated circuit indicating that the output terminal is to communicate a data state, driving said output terminal to a logic level by turning on the one of said pull-up and pull-down transistors corresponding to the data state to be communicated;

latching the logic level at the output terminal;

detecting the initiation of a new cycle of said functional circuitry;

responsive to said detecting step, turning off the one of said pull-up and pull-down transistors turned on in said driving step;

after the turning off step, turning on the one of said pull-up and pull-down transistors that is biased to drive the output terminal to the opposite logic level from that latched in the latching step; and

responsive to said output terminal reaching a selected voltage between said power supply voltage and said reference voltage, turning off the one of said pull-up and pull-down transistors turned on in the turning on step.

23. The method of claim 22, further comprising:

after the turning off step, monitoring the voltage at the output terminal; and

responsive to said monitoring indicating that the voltage at the output terminal has changed by a selected amount, turning back on the one of said pull-up and pull-down transistors turned on in the turning on step, until the output terminal again reaches the selected voltage.