Method for verifying circuit layout design

• US 5,450,331 A
• Filed: 01/24/1992
• Issued: 09/12/1995
• Est. Priority Date: 01/24/1992
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Lin, Pei, Duprez, Herve G.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US07/825,490
• Time in Patent Office: 1,327 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578, 371/23, 395/500
• US Class Current: 716/112
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

The present invention is directed to methods to assist designing integrated circuits by verifying that design constraints (e.g., minimum path width) are satisfied between two arbitrary nodes of a circuit layout. In an exemplary embodiment, a method for designing an integrated circuit layout by verifying that predetermined design constraints are satisfied for an arbitrary path defined by at least two nodes, comprises the steps of labeling all polygons of the integrated circuit layout with a name which corresponds to a layer of the integrated circuit layout in which each polygon is located, creating a file of polygons which includes polygons located along the arbitrary path, and determining whether polygons located along the arbitrary path satisfy predetermined design constraints specified for that path.

Claims

1. Method for designing an integrated circuit layout by verifying that predetermined design constraints are satisfied for a conductive path between at least two nodes, comprising the steps of:

labeling all polygons of said integrated circuit layout with a name which corresponds to a layer of the integrated circuit layout;

creating a file of polygons which includes polygons located along said conductive path; and

determining whether polygons in said file of polygons located along said conductive path satisfy predetermined width constraints specified for that path.

2. Method according to claim 1, wherein said step of creating further includes a step of:

identifying a layer of said integrated circuit layout which includes said at least two nodes; and

building a file of polygons included in said layer.

3. Method according to claim 2, wherein said step of building further includes the steps of:

sorting and merging said file of polygons to identify those polygons which contact one another.

4. Method according to claim 3, wherein said step of determining further includes the steps of:

verifying those paths defined by said merged polygons in said layer which comply with said predetermined width constraints; and

eliminating portions of said merged polygons which fail to comply with said predetermined width constraints.

5. Method according to claim 4, wherein said step of determining further includes the step of:

labeling any remaining portions of said merged polygons with an index for each unconnected node.

6. Method according to claim 5, wherein said step of labeling further includes the step of:

automatically scanning said remaining portions to identify root polygons; and

merging all connected polygons to identify any unconnected nodes, each of said unconnected nodes being associated with only one root polygon upon completion of said scanning, with each root polygon representing a unique index.

7. Method according to claim 5, wherein said step of determining further includes the step of:

locating said at least two nodes relative to said remaining portions; and

comparing the index for any remaining portion corresponding to a first of said at least two nodes with the index for any remaining portion corresponding to a second of said at least two nodes.

8. Method according to claim 7, further including a step of:

indicating verification of minimum path width for said conductive path if the unique indices for any remaining portions corresponding to said first and said second nodes match.

9. Method according to claim 7, further including a step of:

indicating an error in minimum path width for said conductive path if the indices for any remaining portions corresponding to said first and said second nodes do not match.

10. Method for designing an integrated circuit layout by verifying that predetermined design constraints are satisfied for an arbitrary path defined by at least two nodes, comprising the steps of:

labeling all polygons of said integrated circuit layout with a name which corresponds to a layer of the integrated circuit layout in which each polygon is located.;

creating a file of polygons located along said arbitrary path; and

determining whether polygons in said file of polygons located along said arbitrary path satisfy predetermined width constraints specified for that path wherein said step of determining further includes the steps of;

verifying those paths defined by said merged polygons in said layer which comply with said predetermined width constraints;

eliminating those portions of said merged polygons which fail to comply with said predetermined width constraints;

labeling any remaining portions of said merged polygons with an index for each unconnected node;

locating said at least two nodes relative to said remaining portions; and

comparing the index for any remaining portion corresponding to a first of said at least two nodes with the index for any remaining portion corresponding to a second of said at least two nodes.

11. Method according to claim 10, wherein said step of creating further includes a step of:

identifying a layer of said integrated circuit layout which includes said at least two nodes; and

building a file of polygons included in said layer.

12. Method according to claim 11, wherein said step of building further includes the steps of:

sorting and merging said file of polygons to identify those polygons which contact one another.

13. Method according to claim 12, wherein said step of labeling further includes the step of:

automatically scanning said remaining portions to identify root polygons; and

merging all connected polygons to identify any unconnected nodes, each of said unconnected nodes being associated with only one root polygon upon completion of said scanning, with each root polygon representing one of said indices.

14. Method according to claim 12, further including a step of:

indicating verification of minimum path width for said conductive path if the indices for any remaining portions corresponding to said first and said second nodes match.

15. Method according to claim 12, further including a step of:

indicating an error in minimum path width for said conductive path if the indices for any remaining portions corresponding to said first and said second nodes do not match.