Partial-scan built-in self-testing circuit having improved testability

• US 5,450,414 A
• Filed: 05/17/1993
• Issued: 09/12/1995
• Est. Priority Date: 05/17/1993
• Status: Expired due to Term

• Current Assignee: AT&T IPM Corp. (AT&T, Inc.)
• Original Assignee: AT&T Corporation (AT&T, Inc.)
• Inventors: Lin, Chih-Jen
• Primary Examiner(s): Voeltz, Emanuel T.
• Assistant Examiner(s): Tran, Alan
• Application Number:
  US08/063,191
• Time in Patent Office: 848 Days
• Field of Search: 371/22.3, 371/23, 371/22.1, 371/25.1, 371/27, 324/158 R, 324/73.1, 324/158 P, 324/158 F, 29/825, 29/846, 29/832
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318342 by preliminary fault modelling, e.g. analysis, simulation
• CPC Class Codes: G01R 31/318583 Design for test
• CPC Class Codes: G01R 31/318586 with partial scan or non-scannable parts

Abstract

The testability of a near-acyclic circuit (14) can be enhanced by the addition of one or more control points (36) and observation points (34) to allow for increased observability and controllability of selected nodes (28). The control points (36) and/or test points (34) are added by first computing the controllability, observability and fault detection probability at each node. A fault is then selected. If either the controllability or observability for such fault is not inside a prescribed value range, and the fault detection probability is below a prescribed value, then either a control point (36) and/or a observation point (34) may be added.

Claims

1. A digital circuit having an improved ability to be electronically tested by test signals applied thereto comprising:

a sequential network having a near-acyclic structure, the network having at least one node therein at which a fault may occur;

a test pattern generator coupled to the network for supplying successive test patterns thereto to cause the network to generate a response following receipt of each successive pattern;

an electronic logic block coupled to the network for compacting the response generated thereby; and

the digital circuit being characterized by at least one test point added within the sequential network to improve the testability thereof, the test point being added at a node selected such that the node has a separate one of its controllability and observability probabilities different from a prescribed value therefor and a detection probability below a prescribed value therefor prior to the addition of the test point, and insertion of the mode increases fault coverage during testing.

2. The circuit according to claim 1 wherein the test point comprises an observation point.

3. The circuit according to claim 1 wherein the test point comprises a control point.

4. The circuit according to claim 3 wherein the control point comprises an OR gate when the selected node has a controllability below a prescribed value.

5. The circuit according to claim 3 wherein the control point comprises an AND gate when the selected node has a controllability above a prescribed value.

6. A method for modifying a near-acyclic circuit to improve its testability by adding at least one test point thereto to increase the level of fault coverage when the circuit is tested by applying a successive one of t random test patterns thereto, comprising the steps of:

(a) computing the controllability, observability and detection probabilities of each node in the circuit;

(b) selecting a fault for a given one of the nodes;

(c) adding a test point at a particular node when a separate one of the controllability and observability probabilities for the node is not within a prescribed value range for each value therefor and the detection probability is below a prescribed value therefor; and

(d) repeating the steps of (a)-(c) until either the fault coverage no longer increases or until no more faults can be selected.

8. The method according to claim 6 wherein the test point which is added comprises a control point.

9. The method according to claim 8 wherein the control point comprises an AND gate when the controllability of the node at which the control is to be added is above a prescribed value.

10. The method according to claim 8 wherein the control point comprises an OR gate when the controllability of the node at which the control is to be added is below a prescribed value.

11. The method according to claim 6 wherein only control points are added as long as no more faults can be selected and thereafter repeating steps (a)-(c), wherein either control points or observation points are added.

12. The method according to claim 6 wherein the controllability of each node in the circuit is computed by the steps of:

(a) decomposing the circuit into serf-loop flip-flop blocks, each containing a self-looping flip-flop and primary output blocks containing no self-looping flip-flops;

(b) replace each non-self-loop flip-flop with a short circuit;

(c) computing the controllability of each self-loop flip-flop block from a lower macro-level toward a higher macro-level, one block at a time, by the steps of;

(i) assigning a controllability value to the Q output of the self-looping flip-flop in the block to zero and then computing the controllability of all nodes in the block, including the controllability (C(0)) of the corresponding flip-flop D input;

(ii) assigning a controllability value of one to the Q outputs of the self-looping flip-flop and then updating the controllability of each node lying in the path of the self-looping flip-flop and an input of a gate in the block connected to the output of the self-looping flip-flop to reflect the controllability change at the self-looping flip-flop Q output, with the new controllability at the self-looping flip-flop D input now being C(1);

(iii) assigning the value of C(0)/(1-C(1)+C(0)) to the controllability of the Q output of the self looping flip-flop and then updating the controllabilities of said nodes lying in the path of the self-looping flip-flop and an input of a gate in the block connected to the output of the self-looping flip-flop; and

(d) computing the controllability of each primary output block from a lower macro-level to a higher macro-level, one block at a time.

13. The method according to claim 6 wherein the observability of each node in the circuit is computed by the steps of:

(a) decomposing the circuit into self-loop flip-flop blocks, each containing a self-looping flip-flop and primary output blocks containing no self-looping flip-flops; and

(b) computing the observability of each primary output block;

(c) computing the observability of each self-loop flip-flop block by the steps of;

(i) Assign O(W), the observability of each self-loop flip-flop block, to the O(Q), the observability of the Q output of the self-loop flip-flop in the block if there exists a branch W which link the block somewhere else;

otherwise assign zero to O(Q);

(ii) Assign O(Q) to O(D), the observability of the D input of the self-loop flip-flop in the block 32;

(iii) Compute only the observabilities of each node lying in the path of the self-looping flip-flop and an input of a gate in the block connected to the output of the self-looping flip-flop in the block from the self-loop flip-flop D input back to each preceding node, until O(B), the observability along a feedback loop B in the block is computed;

(iv) Calculate the O(Q) using the relationship;

space="preserve" listing-type="equation">O(Q)=1-[(1-O(B))*(1-O(W))]

(v) Calculate if O(Q)-O(D)/(O(D))>

a prescribed % then repeat step (ii);

otherwise

(vi) Assign O(Q) to O(D); and

(vii) Compute the observability of all of the nodes in the self-loop flip-flop.

14. The method to claim 6 wherein the detection probability for a fault at a node is computed in accordance with the controllability and observability for that node.

7. The method according to 6 wherein the test point which is added comprises an observation point.