Semiconductor memory device with error checking and correcting function

• US 5,450,424 A
• Filed: 05/24/1993
• Issued: 09/12/1995
• Est. Priority Date: 07/27/1992
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Okugaki, Akira, Kohda, Kenji, Makihara, Hiroyasu
• Primary Examiner(s): Trammell, James P.
• Application Number:
  US08/065,301
• Time in Patent Office: 841 Days
• Field of Search: 365/103-105, 365/174-188, 365/189.1-189.12, 365/200, 371/10.1-10.3, 371/21.1, 371/40.1, 395/400
• US Class Current: 714/772
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems

Abstract

A memory cell array is divided into a plurality of subregions along row and column directions. In data reading, 1-bit memory cell is selected from each of the subregions which are arranged on different rows and different columns in this memory cell array. Data are simultaneously read from the simultaneously selected memory cells. The simultaneously read data include information bits and at least one error checking bit. Only data of a 1-bit memory cell is read from one word line at the maximum. Thus, it is possible to extremely reduce a probability that two or more erroneous data bits are included in a plurality of bits of simultaneously read data even if a selected word line is defective. It is possible to execute error checking and correction in accordance with an ECC scheme, improving repairability for defective bits in a semiconductor memory device.

Claims

1. A semiconductor memory device comprising:

a memory cell array including a plurality of memory cells arranged in rows and columns;

selection means responsive to an address signal for simultaneously selecting a predetermined constant number of memory cells in said memory cell array, each of the simultaneously selected memory cells being arranged both on a different row and on a different column with respect to other selected memory cells in said memory cell array for any address designated by said address signal; and

reading means for reading out data of all of the simultaneously selected memory cells.

2. A semiconductor memory device according to claim 1, wherein said selection means includes:

row selection means responsive to a row address for simultaneously selecting a plurality of rows in said memory array; and

cell selection means responsive to block and column addresses for simultaneously selecting memory cells on respective selected rows and on different columns.

3. A semiconductor memory device according to claim 1, wherein said memory cell array includes a plurality of subregions arranged in row and column directions, each said subregion including a plurality of memory cells arranged in rows and columns, and

wherein said selection means includes:

means responsive to an address for activating a predetermined number of subregions among said subregions to bring the memory cells in the selected subregions into a selected state, said selected predetermined number of subregions being arranged on different rows and different columns with each other, and

cell selection means responsive to a column address for selecting a plurality of memory cells, one from each of the selected predetermined number of subregions for data reading.

4. A semiconductor memory device according to claim 1, wherein said memory cell array provides the storage for information bits and at least one error checking and correction bit, and wherein the number of said simultaneously selected memory cells is equal to the sum of the numbers of the information bits and said at least one error checking and correcting bit.

5. A semiconductor memory device according to claim 1, wherein said memory cell array is divided into a plurality of subregions in row and column directions, and

wherein said memory cell comprises a memory transistor having one conduction terminal coupled to a bit line corresponding a column, another conduction terminal coupled to a source line, and a gate connected to a word line corresponding to a row and for nonvolatilely storing a data, and

wherein said selection means including block selection means responsive to the address signal for selecting a plurality of subregions arranged on different rows and different columns in said memory cell array, and means responsive to said block selection means for forming a current flow path from a bit line through a memory cell on a selected row and a source line to a reference potential supply only in the selected subregions.

6. A semiconductor memory device comprising:

a memory cell array including nonvolatile memory cells being arranged in a matrix of rows and columns, said memory cell array being divided into the same number of blocks along directions of said rows and said columns to have a plurality of subregions;

a plurality of word lines being arranged in correspondence to said rows of said memory cell array, each said word line being connected with a row of said memory cells;

a plurality of bit lines being arranged in correspondence to said columns of said memory cell array, each said bit line being coupled with a column of said memory cells;

a plurality of sub source lines each being coupled with a prescribed number of cells of said memory cells;

a plurality of main source lines being arranged in correspondence to respective said subregions, each said main source line being connected with sub source lines provided in a corresponding subregion in common;

word line selection means for selecting a plurality of word lines included in different subregions in said column direction in response to a supplied address signal;

source line selection means for simultaneously selecting a plurality of main source lines being provided in different subregions in said row and column directions from said plurality of subregions in response to the supplied address signal;

bit line selection means for selecting a plurality of bit lines one from each of said subregion being divided in said row direction in response to the supplied address signal; and

means for reading data from memory cells being arranged in correspondence to intersections of the selected word lines, the selected bit lines and the sub source lines being connected to the selected main source lines.

7. A semiconductor memory device according to claim 6, wherein a predetermined number of memory cells are connected in series between an associated bit line and an associated sub source line to constitute a memory unit, and wherein said source line selection means includes coupling means for coupling the main source line in each respective selected subregion to a reference potential supply and for bringing main source lines in non-selected subregions into an electrically floating state.

8. A semiconductor memory device according to claim 7, wherein said coupling means includes means for coupling all the sub source lines in the selected subregions to the reference potential supply.

9. A semiconductor memory device according to claim 7, wherein said coupling means includes means for coupling a sub source line for a memory unit crossing a selected word line to the reference potential supply through the main source lines.

10. A semiconductor memory device comprising:

a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns for storing information in a nonvolatile manner, a prescribed number of cells of said memory cells being serially arranged to form a unit, said memory cell array being divided into a plurality of regions along directions of said rows and said columns;

a plurality of word lines arranged in correspondence to respective said rows;

a plurality of bit lines arranged in correspondence to respective said columns;

a plurality of source lines arranged in correspondence to said prescribed number of memory cells, each said unit having said prescribed number of memory cells serially connected between a corresponding source line and a corresponding bit line;

word line selection means for simultaneously selecting a plurality of word lines contained in different ones of said regions divided along said column direction from said plurality of word lines in response to a supplied address;

bit line selection means for selecting a bit line from respective ones of said regions divided along said row direction in response to the supplied address signal; and

source line selection means for forming a current path between a corresponding bit line and a corresponding source line for each of said units of said memory cells in response to the supplied address, said source line selection means including means for forming said current paths for the units of said memory cells provided in different subregions from each other in both said row and column directions.

11. A semiconductor memory device in accordance with claim 10, wherein said source selection means includes:

decoder means for selecting a plurality of subregions in response to a row address signal and a column address signal and generating signals for specifying memory cell units in the selected subregions, and

means provided in correspondence to said memory cell units for connecting corresponding memory cell units to corresponding bit or source lines in response to outputs of said decoder means to form said current paths between said corresponding bit lines and said corresponding source lines.

12. A semiconductor memory device in accordance with claim 10, wherein said source line selection means includes:

first decoder means for generating a bit line specifying signal for specifying a bit line in response to a supplied address signal,

a first switching element for forming a current path between the specified bit line and an associated source line in a unit of a memory cell unit in response to an output of said first decoder means,

second decoder means for generating a signal for specifying a subregion in response to a supplied address, and

a second switching element for forming said current paths between bit lines and corresponding source lines with respect to all of memory cell units in the specified subregions in response to an output of said second decoder means,

said first switching element, said second switching element and a memory cell unit being connected in series between a corresponding bit line and a corresponding source line.

13. A method of reading out data from a semiconductor memory device having a memory cell array including a plurality of memory cells arranged in rows and columns, comprising the steps of:

selecting a plurality of rows in said memory cell array in response to a first address signal;

selecting a plurality of memory cells on the selected rows and on different columns in response to a second address signal, one memory cell from each of the selected rows, each of the selected memory cells being arranged on a different column with respect to other selected memory cells for any address designated by said second address signal;

reading data of the selected memory cells for error checking and correction; and

supplying data externally after the error checking and correction.

14. A method according to claim 13, wherein said memory cell array includes a plurality of rows blocks, each sharing a row, and a plurality of column blocks, each sharing a column, and

wherein said first mentioned step of selecting includes the steps of selecting a row in each respective row block, and activating a sub block in said each respective row block such that each activated sub block is contained in a different column block from other activated sub blocks.

15. A method according to claim 14, wherein the second mentioned step of selecting includes the step of selecting a column in each respective column block.

16. A method according to claim 14, wherein said memory cell comprises a nonvolatile memory cell transistor, and wherein said step of activating includes the step of establishing a current flow path through a memory cell transistor from an associated column to a reference potential supply in the activated subregions.