Method and apparatus for phase-aligned multiple frequency synthesizer with synchronization window decoder

• US 5,450,458 A
• Filed: 08/05/1994
• Issued: 09/12/1995
• Est. Priority Date: 08/05/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Price, Warren E., Uplinger, Kenneth A.
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US08/286,822
• Time in Patent Office: 403 Days
• Field of Search: 375/354, 375/356, 375/371, 375/373, 375/376, 370/100.1, 370/105.3, 326/93, 327/105, 327/107, 327/141, 327/144, 327/145
• US Class Current: 375/356
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Abstract

Data transfer between subsystems of an information handling system employing a multiple subsystem clock environment architecture, or between multiple information handling systems operating with different clock frequencies, is synchronized using a timing aligned multiple frequency synthesizer with a synchronization window decoder. A frequency generation circuit in circuit communication with a data synchronization circuit functions to produce a synchronized timing signal(s) to permit a central processing unit operating in one subsystem clock environment to function with a peripheral subsystem(s), such as a memory controller, operating in a different subsystem clock environment, or permits information handling systems operating with different clock frequencies to function with one another. Data transfer synchronization delays are reduced and mean-time-to-failure of signal synchronization accuracy is increased by eliminating metastability effects from the synchronization circuitry.

Claims

1. An apparatus for synchronizing data transfer from a first system operating responsive to a first frequency clock signal to a second system operating responsive to a second frequency clock signal, comprising:

(a) means for generating said first frequency clock signal and said second frequency clock signal at a fixed predetermined timing relationship relative to one-another over a clock frame period to minimize synchronization setup time and hold time;

(b) means for decoding the fixed predetermined timing relationship between said second frequency clock signal and said first frequency clock signal during the clock frame period;

(c) means for generating a sync enable signal responsive to the decoded fixed predetermined timing relationship, said sync enable signal indicating that a first system bus validity signal satisfies valid setup time and hold time requirements relative to said second frequency clock signal;

(d) means for generating a synchronization signal by clocking said first system bus validity signal on the next clock edge of said second frequency clock signal as qualified by said sync enable signal; and

(e) means for transferring data from said first system to said second system responsive to said synchronization signal.

2. A method of synchronizing data transfer from a first system operating responsive to a first frequency clock signal to a second system operating responsive to a second frequency clock signal, comprising the steps of:

(a) generating said first frequency clock signal and said second frequency clock signal at a fixed predetermined timing relationship relative to one-another over a clock frame period to minimize synchronization setup time and hold time;

(b) decoding the fixed predetermined timing relationship between said second frequency clock signal and said first frequency clock signal during the clock frame period;

(c) generating a sync enable signal responsive to said decoded timing relationship, said sync enable signal indicating that a first system bus validity signal satisfies valid setup time and hold time requirements relative to said second frequency clock signal;

(d) generating a synchronization signal by clocking said first system bus validity signal on the next clock edge of said second frequency clock signal as qualified by said sync enable signal; and

(e) transferring data from said first system to said second system responsive to said synchronization signal.

3. An information handling system having subsystems operating at different clock frequencies and being capable of transferring data between those subsystems, comprising:

(a) a first subsystem requiring for its operation a first clock signal at a first predetermined frequency, and having a bus associated therewith, said first subsystem being configured to operate as a data send subsystem and as a data receive subsystem;

(b) a second subsystem in circuit communication with said first subsystem via the bus and requiring for its operation a second clock signal at a second predetermined frequency, said second subsystem being configured to operate as a data send subsystem and as a data receive subsystem;

(c) a timing circuit in circuit communication with said first subsystem and said second subsystem and responsive to a reference clock signal, said timing circuit being configured to generate timing pulses for operation of the information handling system;

(d) a clock generation circuit in circuit communication with said first subsystem and said second subsystem and responsive to the timing pulses of said timing circuit, and being configured to generate (i) said first clock signal and said second clock signal at a fixed predetermined timing relationship relative to one-another over a clock frame period to minimize synchronization setup time and hold time, and (ii) a first sync pulse for signalling timing information and a second sync pulse for signalling timing information;

(e) a first synchronization window decoder circuit in circuit communication with said clock generation circuit and responsive to said first clock signal and said first sync pulse, and being configured to decode the predetermined timing relationship between said first clock signal and said second clock signal during the clock frame period, and being configured to generate a first sync enable signal, said first sync enable signal being used to signal that a second subsystem bus validity signal satisfies valid setup time and hold time requirements relative to said first clock signal;

(f) a first synchronization circuit in circuit communication with said first subsystem, said clock generation circuit, and said first synchronization window decoder circuit, and responsive to said first clock signal, said first sync enable signal, and said second subsystem bus validity signal, and being configured to generate a first synchronization signal by clocking said second subsystem bus validity signal on the next clock edge of said first clock signal as qualified by said first sync enable signal, said first synchronization signal being used to control data transfer from said second subsystem to said first subsystem;

(g) a second synchronization window decoder circuit in circuit communication with said clock generation circuit and responsive to said second clock signal and said second sync pulse, and being configured to decode the predetermined timing relationship between said second clock signal and said first clock signal during the clock frame period, and being configured to generate a second sync enable signal, said second sync enable signal being used to signal that a first subsystem bus validity signal satisfies valid setup time and hold time requirements relative to said second clock signal;

(h) a second synchronization circuit in circuit communication with said second subsystem, said clock generation circuit, and said second synchronization window decoder circuit, and responsive to said second clock signal, said second sync enable signal, and said first subsystem bus validity signal, and being configured to generate a second synchronization signal by clocking said first subsystem bus validity signal on the next clock edge of said second clock signal as qualified by said second sync enable signal, said second synchronization signal being used to control data transfer from said first subsystem to said second subsystem; and

(i) a data transfer device in circuit communication with said first subsystem, said second subsystem, said first synchronization circuit, and said second synchronization circuit, said data transfer device being configured to transfer data between said first subsystem and said second subsystem via the bus, the transfer of data from said second subsystem to said first subsystem being responsive to said first synchronization signal and the transfer of data from said first subsystem to said second subsystem being responsive to said second synchronization signal.

4. The information handling system of claim 3, wherein said first subsystem comprises a system processor and wherein said second subsystem comprises a peripheral device.

5. The information handling system of claim 3, wherein said timing circuit comprises a phase-locked loop frequency synthesizer for generating timing pulses for operation of the information handling system.

6. The information handling system of claim 3, wherein said clock generation circuit comprises a waveform sequencer for generating (i) said first clock signal and said second clock signal at the fixed predetermined timing relationship relative to one-another over the clock frame period to minimize synchronization setup time and hold time, and (ii) said first sync pulse for conveying timing information and said second sync pulse for conveying timing information.

7. The information handling system of claim 3, wherein said first clock signal and said second clock signal are aligned such that periodically said first clock signal and said second clock signal have rising edges that are substantially aligned.

8. The information handling system of claim 7, wherein said first synchronization signal becomes active responsive to the rising edges of said first clock signal, and said second clock signal being substantially aligned and said second synchronization signal becomes active responsive to the rising edges of said second clock signal and said first clock signal being substantially aligned.

9. The information handling system of claim 3, wherein said first clock signal and said second clock signal are aligned such that periodically said first clock signal and said second clock signal have falling edges that are substantially aligned.

10. The information handling system of claim 9, wherein said first synchronization signal becomes active responsive to the falling edges of said first clock signal and second clock signal being substantially aligned, and said second synchronization signal becomes active responsive to the falling edges of said second clock signal and said first clock signal being substantially aligned.

11. The information handling system of claim 3, wherein said bus comprises a system processor bus, and further comprising a peripheral bus interface associated with said second subsystem, said peripheral bus interface being in circuit communication with said first subsystem via said system processor bus.

12. The information handling system of claim 3, wherein said first subsystem bus validity signal defines the start of a first subsystem bus cycle in response to a first subsystem bus signal satisfying valid delay time requirements and said second subsystem bus validity signal defines the start of a second subsystem bus cycle in response to a second subsystem bus signal satisfying valid delay time requirements.

13. The information handling system of claim 12, wherein said first subsystem comprises a central processing unit, said bus comprises a system processor bus, said first subsystem bus validity signal comprises an address strobe signal generated by said central processing unit responsive to designated signals on predetermined lines of said system processor bus currently satisfying valid delay time requirements, and further comprising a peripheral bus interface associated with said second subsystem, said peripheral bus interface being in circuit communication with said first subsystem via said system processor bus.

14. The information handling system of claim 13, wherein said second subsystem comprises a memory controller and said second subsystem bus validity signal comprises a ready signal generated by said memory controller responsive to designated signals on predetermined lines of said peripheral bus interface currently satisfying valid delay time requirements.

15. A method of signal synchronization for an information handling system having a first subsystem operating responsive to a first clock signal at a first predetermined frequency and a second subsystem operating responsive to a second clock signal at a second predetermined frequency, and being capable of transferring data between one-another, comprising the steps of:

(a) generating (i) the first clock signal at the first predetermined frequency and the second clock signal at the second predetermined frequency, the first clock signal and the second clock signal having a fixed predetermined timing relationship relative to one another over a clock frame period to minimize synchronization setup time and hold time, and (ii) a first sync pulse for signalling timing information and-a second sync pulse for signalling timing information;

(b) decoding the predetermined timing relationship between said first clock signal and said second clock signal during the clock frame period responsive to said first clock signal and to said first sync pulse;

(c) generating a first sync enable signal responsive to said first clock signal and to said first sync pulse to signal that a second subsystem bus validity signal satisfies valid setup time and hold time requirements relative to said first clock signal;

(d) generating a first synchronization signal by clocking said second subsystem bus validity signal on the next clock edge of said first clock signal as qualified by said first sync enable signal, said first synchronization signal being used to control data transfer from said second subsystem to said first subsystem;

(e) decoding the predetermined timing relationship between said second clock signal and said first clock signal during the clock frame period responsive to said second clock signal and to said second sync

(f) generating a second sync enable signal responsive to said second clock signal and to said second sync pulse to signal that a first subsystem bus validity signal satisfies valid setup time and hold time requirements relative to said second clock signal;

(g) generating a second synchronization signal by clocking said first subsystem bus validity signal on the next clock edge of said second clock signal as qualified by said second sync enable signal, said second synchronization signal being used to control data transfer from said first subsystem to said second subsystem; and

(h) transferring data (i) from said first subsystem to said second subsystem responsive to said second synchronization signal, and (ii) from said second subsystem to said first subsystem responsive to said first synchronization signal.