Multi-channel image array buffer and switching network

• US 5,450,549 A
• Filed: 02/16/1995
• Issued: 09/12/1995
• Est. Priority Date: 04/09/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Casparian, Mark A.
• Primary Examiner(s): Harrell, Robert B.
• Assistant Examiner(s): LEDELL, BRAIN
• Application Number:
  US08/389,450
• Time in Patent Office: 208 Days
• Field of Search: 395/250
• US Class Current: 345/556
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence
• CPC Class Codes: H04N 1/32358 using picture signal storage, e.g. at transmitter H04N1/17 takes precedence
• CPC Class Codes: H04N 1/32443 with asynchronous operation of the image input and output devices connected to the memory
• CPC Class Codes: H04N 1/32448 Controlling data flow to or from the memory in relation to the available memory capacity
• CPC Class Codes: H04N 2201/329 Storage of less than a complete document page or image frame
• CPC Class Codes: H04N 5/0736 using digital storage buffer techniques
• CPC Class Codes: H04N 5/4448 for frame-grabbing
• CPC Class Codes: H04N 5/907 using static stores, e.g. storage tubes or semiconductor memories H04N5/91 takes precedence

Abstract

A multi-port buffer stores digitized image and/or audio information from a video camera and transfers the stored image information to a plurality of output channels. Digitized input data is passed through a crossbar switch and stored in a random access memory (RAM). The image data is retrieved from RAM and passed the crossbar switch to one of a plurality of first-in, first-out (FIFO) registers. Raster scan lines are passed from the FIFO registers to corresponding output channels. The order and rate of writing to RAM and reading out to the FIFO registers is controlled by an asynchronous queuing arbiter. If one of the output channels is slower than the others or operates at a variable clock speed, the asynchronous queuing arbiter changes the order in which the FIFO registers are filled to accommodate that output channel. Should one of the output channels fail, the bus request for the corresponding FIFO register is disabled, thereby skipping the failed channel.

Claims

1. A high performance asynchronous input/output video image buffer for providing multiple image frames asynchronously and simultaneously to a plurality of video image output devices in parallel, said video image buffer comprising:

a single input means for receiving a plurality of digitized video input signals from one or more sources;

random access memory means for storing said digitized video input signals;

a plurality of first-in, first-out registers for temporarily storing data read out of said random access memory means, each of said plurality of first-in, first-out registers having a capacity greater than a predefined quantity of data and generates an empty flag when empty and an almost empty flag when said predefined quantity of data has been read out;

write address means for generating write addresses for said random access memory means;

read address means for generating read addresses for said random access memory means;

address switching means for muting write and read addresses to said random access memory means;

data switching means for routing said received video signals into write addressed locations of said random access memory means and for routing data read out of said random access memory means to said plurality of first-in, first-out registers;

asynchronous queuing arbiter means responsive to said plurality of first-in, first-out registers for controlling said address and data switching means, said asynchronous queuing arbiter means being responsive to said empty and almost empty flags to respectively begin to read a new frame of data into a corresponding register or to refill the register from a continuing frame of data read out of said memory means, the order and rate at which data is read out of the memory means to the first-in, first-out registers being controlled by said asynchronous queuing arbiter by monitoring flags from the first-in, first-out registers; and

output means connected to said plurality of first-in, first-out registers for simultaneously transferring parallel data frames, from said first-in, first-out registers to a plurality of output channels asynchronously and in parallel, wherein if one of the output channels is slower than the others or operates at a variable clock speed, the asynchronous queuing arbiter means changes the order in which the first-in, first-out registers are filled to accommodate that output channel.

2. The high performance asynchronous input/output buffer recited in claim 1 wherein said address switching means and said data switching means each comprise a crossbar switch and wherein said address switching means crossbar switch and said data switching means crossbar switch perform write and read accesses to said random access memory means at different address locations.

3. The high performance asynchronous input/output buffer recited in claim 1 wherein said asynchronous queuing arbiter means comprises:

a coodinate memory for storing left/right horizontal coordinates and top/bottom vertical coordinates;

a horizontal counter and a vertical counter respectively connected to receive horizontal and vertical data outputs from said coordinate memory;

horizontal and vertical comparators respectively connected to receive outputs from said horizontal and vertical counters and from said coordinate memory, an output of said horizontal comparator being connected to said vertical counter to initiate counting by the vertical counter; and

mask circuit means connected to receive almost empty flags from said first-in, first-out registers and an output from said vertical comparator, whereby said asynchronous queuing arbiter means controls dictates which first-in, first-out register is loaded with a region of interest image data by selecting the appropriate frame coordinates from the coordinate memory.

4. The high performance asynchronous input/output video image buffer recited in claim 1 wherein said plurality of first-in, first-out registers for simultaneously transferring M parallel data frames, each at a rate O_ri, from said first-in, first-out registers to a plurality of M output channels in parallel wherein the combined output rate is

and the following relationship is satisfied:

space="preserve" listing-type="equation">(N)(I.sub.r)≦

(M)(O.sub.r).