Single-chip self-configurable parallel processor

• US 5,450,557 A
• Filed: 06/29/1994
• Issued: 09/12/1995
• Est. Priority Date: 11/07/1989
• Status: Expired due to Fees

• Current Assignee: Intersonics Technology Corporation
• Original Assignee: Loral Aerospace Corp. (MHR Holdings LLC (New York))
• Inventors: Johnson, S. Val, Kopp, Randall L.
• Primary Examiner(s): Coleman, Eric
• Assistant Examiner(s): DONAGHUE, LARRY D
• Application Number:
  US08/269,969
• Time in Patent Office: 440 Days
• Field of Search: 395/800, 395/375, 395/325
• US Class Current: 712/24
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 2207/3888 Wave pipelining, i.e. processing multiple subsequent operand sets asynchronously within each pipeline stage
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence

Abstract

A self-contained, self-configurable cascadable pipelined processor chip (160) is diclosed. The chip contains a computation section (FIGS. 1a-1d) which consists of various types of computation circuits (20-42) that can be software-interconnected in any desired configuration by a set of multiplexers (44-52) whose settings are under the control of a control section (FIG. 2 ). The control section consists of various types of control circuits (60-76) which are also software-interconnectable in any desired configuration under program control. The chip (160) is configured by a very long instruction word and then executes the algorithm defined by that configuration iteratively until stopped. The chip (160) can be programmed to reconfigure itself in response to computation results or other selectable parameters, either in accordance with internally stored configurations or in accordance with configuration information stored in an external random access memory (56, 58). Internal reconfiguration requires no separate reconfiguration time at all, and external reconfiguration can be accomplished in less than 10 μs.

Claims

1. A configurable programmable processor, comprising:

a) a circuit chip;

b) computational circuit means on said chip for performing computations;

c) a plurality of first multiplexer means on said chip for selectively connecting said computational circuit means to iteratively calculate selectable algorithms, each of said first multiplexer means having at least one input and at least one output;

d) a plurality of second multiplexer means on said chip for controlling the interconnections of said first multiplexer means;

e) means enabling any output of any of said first multiplexer means to be selectably directly unidirectionally interconnected with any input of any of said first multiplexer means by said second multiplexer means;

f) latch register means on said chip for supplying, during iterative computations, a plurality of selectable control values to each of said second multiplexer means, said latch register means including means causing said latch register means to be programmable from outside of said chip; and

g) control means on said chip for controlling the selection of said control values by said second multiplexer means independently of any control input from outside said chip.

2. The processor of claim 1, further comprising a control line connected to said second multiplexer means, said second multiplexer means being arranged to switch from one configuration to another by applying to said second multiplexer means on said control line a single address value.

3. The processor of claim 1, further comprising a source of configuration-identifying very long instruction words (VLIWs) connected to said chip from the outside thereof, said control means being arranged to load a plurality of said from said source onto said chip, and to switch said computational circuit means between the configurations identified thereby without any input from outside said chip.

4. The processor of claim 3, in which a predetermined one of said VLIWs is selected by said control means when said computational circuit means are in a predetermined status.

5. The processor of claim 3, in which at least some of said computational means include selectable delay means for delaying by a selectable amount of time the data processed by said computational means, the selection of said delay means being done by said control means.

6. The processor of claim 3, in which said control means are themselves configurable by said VLIWs.

7. The processor of claim 1, in which said first multiplexer means include first-level and second-level multiplexers, said first-level multiplexers having inputs connected to the outputs of said computational circuit means, and outputs connected to said second-level multiplexers;

and said second-level multiplexers having inputs connected to outputs of said first-level multiplexers, and outputs connected to said computational circuit means.

8. The processor of claim 7, in which there is one second-level multiplexer for each input of at least some of said computational circuit means.

9. A configurable programmable processor, comprising:

a) a circuit chip;

b) a plurality of computational circuits disposed on said chip for carrying out individual arithmetic operations,

c) means enabling any output of any of each of said computational circuits to be selectively unidirectionally interconnected with any input of any other of said computational circuits to form selectable computational circuit configurations;

d) a plurality of control circuits disposed on said chip for individually establishing selected interconnections between said computational circuits and controlling their operation, said control circuits being selectively interconnectable with each other to form selectable control circuit configurations;

e) an input for inputting to said chip a plurality of very long instruction words (VLIWs) each defining a specific set of interconnections of said computational circuits and said control circuits; and

f) a set of registers on said chip for storing said VLIWs;

g) said control circuits and computational circuits being arranged to change configurations in response to a predetermined status of said control and computation circuits and in accordance with said VLIWs;

h) whereby said chip is enabled to perform selectable iterative computations without any input from outside said chip.