Pointer for use with a buffer and method of operation

• US 5,450,560 A
• Filed: 12/21/1992
• Issued: 09/12/1995
• Est. Priority Date: 12/21/1992
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Bridges, Jeffrey T., Osborne, Lawrence W.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): KANG, SANG Y
• Application Number:
  US07/994,031
• Time in Patent Office: 995 Days
• Field of Search: 364/715.1, 364/746, 364/784, 364/200, 364/787, 395/250, 395/800, 395/400, 395/425
• US Class Current: 711/200
• CPC Class Codes: G06F 2205/106 Details of pointers, i.e. structure of the address generators
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence
• CPC Class Codes: G06F 7/5055 in which one operand is a constant, i.e. incrementers or decrementers
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3863 using multiple copies of the architectural state, e.g. shadow registers
• CPC Class Codes: G06F 9/3865 using deferred exception handling, e.g. exception flags

Abstract

A pointer (86) has generate circuitry (90), propagate circuitry (90), carry circuitry (90) and detector circuitry (92). The pointer is for use with a buffer to designate one of a plurality of entries of the buffer. The generate circuitry receives a first and a second data word and generates a plurality of local generate functions. One bit of the first data word, second data word, and one of the local generate functions each corresponds to one of the entries of the buffer. Each data bit of the first data word is representative of the eligibility of the pointer to designate an entry. The second data word is representative of the pointer location at a previous time. The propagate circuitry receives the first and second data words and generates a plurality of local propagate functions. Each local propagate function corresponds to one of the entries of the buffer. The carry circuitry is coupled to the generate circuitry and to the propagate circuitry and generates a plurality of carry bits. Each carry bit corresponds to one of the entries of the buffer. The detector circuitry is coupled to the carry circuitry and detects a predetermined pattern within the plurality of carry bits. The output of the detector circuitry is coupled to the second data word. The pointer may be designed in modules. A modular design procedure makes the pointer easily adapted for applications with different size buffers while maintaining the pointer'"'"'s high speed performance.

Claims

1. A pointer for use with a buffer, the pointer operable to designate one of a plurality of entries of the buffer responsive to input data and responsive to a prior designated entry, the pointer comprising:

generate circuitry for receiving a first and a second data word, said first and second data words each comprising a plurality of data bits, one bit of each first and second data word corresponding to one of the entries of the buffer, a logic state of each data bit of the first data word representative of the eligibility of said pointer to designate an entry, said second data word representative of the pointer location at a previous time, said generate circuitry generating a plurality of local generate functions, each local generate function corresponding to one of the entries of the buffer;

propagate circuitry for receiving said first and second data words, said propagate circuitry generating a plurality of local propagate functions, each local propagate function corresponding to one of said entries of said buffer;

carry circuitry coupled to said generate circuitry and to said propagate circuitry, said carry circuitry generating a plurality of carry bits, a first one of said plurality of carry bits being a function of an input carry bit, one of said plurality of local generate functions, and one of said plurality of local propagate functions, a second one of said plurality of carry bits being a function of another of said plurality of carry bits, another of said plurality of local generate functions, and another of said plurality of local propagate functions, each carry bit corresponding to one of the entries of said buffer; and

detector circuitry coupled to said carry circuitry, said carry circuitry for receiving said plurality of carry bits, said detector circuitry detecting a predetermined pattern within said plurality of carry bits, an output of said detector circuitry coupled to said second data word, a position of said predetermined pattern identifying a subsequent position of said pointer location.

2. The pointer of claim 1 further comprising first data word generator receiving a plurality of data sets, each data set corresponding to one entry of said buffer, said first data word generator generating said first data word.

3. The data processor of claim 1 wherein said detector circuitry further comprises circuitry detecting a zero logic level adjacent to a one logic level within said plurality of carry bits.

4. The pointer of claim 3 wherein said carry circuitry further comprises circuitry for coupling one of said plurality of carry bits to said input carry bit.

5. The pointer of claim 4 further comprising latching circuitry for receiving said output of said detector circuitry, said latching circuitry storing said output of the detector circuitry, said output of the detector circuitry coupled to said second data word.

6. The pointer of claim 1 wherein said carry circuitry further comprises circuitry for coupling one of said plurality of carry bits to said input carry bit.

7. The pointer of claim 6 further comprising latching circuitry for receiving said output of said detector circuitry, said latching circuitry storing said output of said detector circuitry, said output of the detector circuitry coupled to said second data word.

8. The pointer of claim 1 further comprising latching circuitry for receiving said output of the detector circuitry, said latching circuitry storing said output of said detector circuitry, the output of said detector circuitry coupled to said second data word.

9. A method of incrementing a pointer, the pointer designating one of a plurality of entries of a buffer, each entry comprising a first data bit associated with the entry, the data bit representative of the eligibility of the associated entry to be designated, the method comprising the steps of:

generating a plurality of local generate functions, each of said local generate functions receiving two input bits, said first input bit coupled to one of said first data bits, the second input bit coupled to one bit of a plurality of second input bits, a logic state of each one of said plurality of first input bits representative of the eligibility of a pointer to designate an entry, said plurality of second input bits representative of said pointer location at a previous time, each of said plurality of local generate functions corresponding to one of said entries of said buffer;

generating a plurality of local propagate functions, each of said plurality of local propagate functions receiving two input bits, said first input bit coupled to one of said first data bits, the second input bit coupled to one bit of said plurality of second input bits, each of said plurality of local propagate function corresponding to one of said entries of said buffer;

generating a plurality of carry bits, each one of said plurality of carry bits corresponding to one of said entries of said buffer, a first one of said plurality of carry bits being a function of an input carry bit, one of said plurality of local generate functions, and one of said plurality of local propagate functions, a second one of said plurality of carry bits being a function of another of said plurality of carry bits, another of said plurality of local generate functions, and another of said plurality of local propagate functions; and

detecting a predetermined pattern within said plurality of carry bits, a position of said predetermined pattern identifying a subsequent position of said pointer.

10. The method of claim 9 wherein said step of detecting further comprises the step of detecting a zero to one transition within said plurality of carry bits.

11. The method of claim 10 wherein said step of generating a plurality of carry bits further comprises the step of coupling said input carry bit to another of said plurality of carry bits.

12. The method of claim 11 further comprising the step of latching said position of said predetermined pattern.

13. The method of claim 9 wherein said step of generating a plurality of carry bits further comprises the step of coupling said input carry bit to another of said plurality of carry bits.

14. The method of claim 13 further comprising the step of latching said position of said predetermined pattern.

15. The method of claim 9 further comprising the step of latching said position of said predetermined pattern.