Reducing pipeline delays in compilers by code hoisting
First Claim
Patent Images
1. A method in a data processing system for improving utilization of clock cycles for a sequence of computer instructions, comprising:
- a. representing, by said data processing system, said computer instructions in a control flowgraph, said control flowgraph comprising at least one subgraph, said at least one subgraph comprising at least one parent texture, said at least one parent texture having at least one child node related thereto;
b. searching, by said data processing system, said control flowgraph to identify subgraphs which are textures of order at least two;
c. for any identified subgraph;
i. examining, by said data processing system, instructions in at least one child node of said identified subgraph;
ii. determining, by said data processing system, whether each instruction is hoistable; and
iii. if said instruction is hoistable, merging, by said data processing system, said instruction from said child node to its parent texture.
0 Assignments
0 Petitions
Accused Products
Abstract
This invention permits an optimizing compiler to minimize the effect of pipeline delays, which are typically introduced by branching code. This invention employs code hoisting to introduce computations from lower regions of the flowgraph, into regions where pipeline delays are known to occur.
-
Citations
7 Claims
-
1. A method in a data processing system for improving utilization of clock cycles for a sequence of computer instructions, comprising:
-
a. representing, by said data processing system, said computer instructions in a control flowgraph, said control flowgraph comprising at least one subgraph, said at least one subgraph comprising at least one parent texture, said at least one parent texture having at least one child node related thereto; b. searching, by said data processing system, said control flowgraph to identify subgraphs which are textures of order at least two; c. for any identified subgraph; i. examining, by said data processing system, instructions in at least one child node of said identified subgraph; ii. determining, by said data processing system, whether each instruction is hoistable; and iii. if said instruction is hoistable, merging, by said data processing system, said instruction from said child node to its parent texture. - View Dependent Claims (2, 3, 7)
-
-
4. A method in a data processing system for improving utilization of clock cycles for a sequence of computer instructions, comprising:
-
a. representing, by said data processing system, said computer instructions in a control flowgraph, said control flowgraph comprising at least one subgraph, said at least one subgraph comprising at least one parent texture, said at least one parent texture having at least one child node related thereto; b. searching, by said data processing system, said flowgraph to identify subgraphs which are textures of order at least two; c. for any identified subgraph; i. examining, by said data processing system, instructions in at least one child node of said identified subgraph; ii. dletermining, by said data processing system, whether each instruction is hoistable; and iii. if said instruction is hoistable, merging, by said data processing system, said instruction from said child node to its parent texture; d. continuing steps i) through iii) for each child node until either all candidate instructions from child nodes are exhausted or all delay inherent in said parent is eliminated. - View Dependent Claims (5, 6)
-
Specification