SIMD architecture with transfer register or value source circuitry connected to bus

• US 5,450,603 A
• Filed: 12/18/1992
• Issued: 09/12/1995
• Est. Priority Date: 12/18/1992
• Status: Expired due to Fees

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Davies, Daniel
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): HARRITY, JOHN E
• Application Number:
  US07/993,218
• Time in Patent Office: 998 Days
• Field of Search: 395/800, 395/200, 395/275, 364/133, 364/231.9, 364/260.1, 364/DIG. 1
• US Class Current: 712/22
• CPC Class Codes: G06F 15/17368 non hierarchical topologies
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses

Abstract

A SIMD parallel processor includes two types of circuitry interconnecting its processing units: One kind interconnects the processing units into an array so that each processing unit can transfer data to an adjacent processing unit in the array and can receive data from an adjacent processing unit; the processing units can, for example, be interconnected in a one-dimensional array. Another kind of interconnecting circuitry includes bus circuitry to permit greater freedom in transferring data to and from processing units. Connected to the bus is a register, so that data can be transferred between processing units by first transferring data from one processing unit to the register and by then transferring data from the register to another processing unit. Or data stored in the register can be sent to a subset or to all of the processing units. Similarly, control circuitry can itself provide data on the bus for transfer to one, a subset, or all of the processing units. A bidirectional register can be connected between each processing unit and the bus, so that a processing unit can be selected to provide data to the bus by selecting its bidirectional register. Similarly, each processing unit can include a memory that can be selected with a write enable signal so that a set of processing units can be selected to receive and store in memory data from the bus.

Claims

1. A method of operating a parallel processor that includes:

two or more processing units;

each processing unit including memory circuitry for storing data;

each processing unit'"'"'s memory circuitry storing a

respective set of items of data, each of which can be accessed when the memory circuitry receives a respective address from a set of addresses;

interconnecting circuitry for interconnecting the processing units;

the interconnecting circuitry including;

bus circuitry;

for each processing unit, respective source/destination circuitry connected to the bus circuitry and the processing unit for providing items of data from the processing unit to the bus circuitry and for receiving items of data from the bus circuitry for the processing unit;

the memory circuitry of each processing unit being connected to receive a data item from the processing unit'"'"'s source/destination circuitry; and

a transfer register connected to the bus circuitry for receiving items of data from the bus circuitry, for storing received items of data, and for providing stored items of data to the bus circuitry;

the bus circuitry being capable of transferring an item of data received from the source/destination circuitry of each of the processing units to the transfer register and further being capable of transferring an item of data received from the transfer register to the source/destination circuitry of each of the processing units; and

addressing circuitry connected for providing items of address data to the memory circuitry of each of the processing units in parallel;

the items of address data indicating a series of addresses from the set of addresses;

the method comprising acts of;

providing an item of instruction data indicating a first instruction to the processing circuitry of all of the processing units in parallel;

the processing circuitry of all of the processing units responding by executing the first instruction in parallel;

each processing unit'"'"'s processing circuitry, in executing the first instruction, providing an item of data to the processing unit'"'"'s source/destination circuitry;

the processing circuitry of a first one of the processing units providing a first item of data to the first processing unit'"'"'s source/destination circuitry;

providing first transfer signals to the first processing unit'"'"'s source/destination circuitry so that the first processing unit'"'"'s source/destination circuitry provides the first item of data to the bus circuitry;

providing second transfer signals to the transfer register so that the transfer register receives the first item of data from the bus circuitry and stores the first item of data;

providing third transfer signals to the transfer register so that the transfer register provides the stored first item of data to the bus circuitry;

providing fourth transfer signals to the source/destination circuitry of each processing unit so that the source/destination circuitry of each processing unit receives the first item of data from the bus circuitry;

operating the addressing circuitry to provide an item of address data indicating an address to the memory circuitry of all of the processing units in parallel; and

providing a write enable signal to the memory circuitry of a second one of the processing units;

the memory circuitry of the second processing unit responding to the write enable signal by writing the first item of data from the second processing unit'"'"'s source/destination circuitry at the address indicated by the item of address data provided by the addressing circuitry.

2. The method of claim 1 in which the source/destination circuitry of each processing unit includes a registered transceiver connected to receive a data item from the processing unit;

the act of providing first transfer signals to the first processing unit'"'"'s source/destination circuitry comprising;

providing a select signal to the first processing unit'"'"'s registered transceiver;

the registered transceiver responding to the select signal by providing the first data item to the bus circuitry.