Unified floating point and integer datapath for a RISC processor

• US 5,450,607 A
• Filed: 05/17/1993
• Issued: 09/12/1995
• Est. Priority Date: 05/17/1993
• Status: Expired due to Term

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Kowalczyk, Andre, Yeung, Norman K. P.
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): DONAGHUE, LARRY D
• Application Number:
  US08/063,183
• Time in Patent Office: 848 Days
• Field of Search: 395/800, 395/375
• US Class Current: 712/41
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A 64-bit wide unified integer and floating-point datapath for a RISC processor. The unified datapath allows for the sharing of some of the major hardware resources within the integer and floating-point execution units, as well as simplifying a large portion of the peripheral circuitry. The unified datapath results in a more efficient use of the hardware with reduced average power dissipation and area, without compromising the major performance advantages of RISC processors.

Claims

1. In a reduced instruction set computer (RISC) processor having a multi-stage pipelined datapath, a unified integer and floating-point datapath comprising:

a register file combining a plurality of general purpose registers and a plurality of floating-point registers;

an integer/mantissa execution unit, coupled to said register file, said integer/mantissa execution unit comprising;

an adder,

a shifter,

a Boolean logic functional unit,

a normalization logic unit, and

a multiplexing network selectively routing operands to said adder, shifter, Boolean logic functional unit and normalization logic unit,

an exponent execution unit coupled to said register file; and

a unified control unit incorporating a superset of integer and floating-point instructions, said unified control unit coupled to said integer/mantissa execution unit and said exponent execution unit for controlling the operation and flow of operands through said integer/mantissa and exponent execution units,

wherein said multiplexing network in said integer/mantissa execution unit comprises;

a plurality of shift multiplexers having inputs coupled to receive operands, and having control inputs coupled to said unified control unit;

a booth multiplexer having inputs coupled to outputs of said shift multiplexers, and an output coupled to a first input of said adder;

an add multiplexer having inputs coupled to outputs of said shift multiplexers, and an output coupled to second input of said adder;

a first multiplexer having inputs coupled to an output of said shifter and an output of said Boolean logic functional unit, respectively, a control input coupled to said unified control unit, and an output;

a result multiplexer having a first input coupled to an output of said adder, a second input coupled to an output of said first multiplexer, and a control input coupled to said unified control unit; and

a sum register for temporarily storing an output of said result multiplexer, and for feeding back said output of said result multiplexer to said shift multiplexers.

2. In a reduced instruction set computer (RISC) processor having a multi-stage pipelined datapath, a unified integer and floating point datapath comprising:

a register file combining a plurality of general purpose registers and a plurality of floating-point registers;

an unpacker coupled to said register file;

an integer/mantissa execution unit coupled to said unpacker, comprising;

a plurality of input multiplexers having inputs coupled to receive operands form said unpacker,

a carry-propagate adder having a first and a second input coupled to outputs of said plurality of input multiplexers,

a shifter having an input coupled to an output of said plurality of input multiplexers,

a Boolean logic functional block having inputs coupled to said unpacker,

a first multiplexer having inputs coupled to an output of said shifter and an output of said Boolean logic functional block, respectively, and an output, and

a result multiplexer having a first input coupled to an output of said carry-propagate adder, a second input coupled to an output of said first multiplexer;

an exponent execution unit coupled to said unpacker, comprising;

a first and a second operand multiplexer coupled to receive operands from said unpacker,

a carry-selected adder having a first input and a second input coupled to an output of said first operand multiplexer and an output of said second operand multiplexer, respectively, and

a result multiplexer having two inputs coupled to outputs of said carry-selected adder;

a repacker coupled to outputs of said exponent execution unit and said integer/mantissa execution unit; and

a unified execution control unit coupled to said integer/mantissa execution unit and said exponent execution unit, said unified execution control unit incorporating a superset of integer and floating-point instructions for controlling the operation and flow of operands through said integer/mantissa and said exponent execution units.