Making and testing an integrated circuit using high density probe points

• US 5,451,489 A
• Filed: 04/30/1993
• Issued: 09/19/1995
• Est. Priority Date: 05/16/1988
• Status: Expired due to Fees

• Current Assignee: ELM TECHNOLOGY CORPORATION
• Original Assignee: Glenn J. Leedy
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): Duda, Kathleen
• Application Number:
  US08/055,439
• Time in Patent Office: 872 Days
• Field of Search: 430/311, 430/313, 430/318, 430/30, 430/394, 430/396, 430/296
• US Class Current: 430/313
• CPC Class Codes: G01R 1/06716 Elastic
• CPC Class Codes: G01R 1/06761 related to layers
• CPC Class Codes: G01R 1/07307 with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 1/0735 arranged on a flexible frame or film
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/316 Testing of analog circuits G01R31/2851 takes precedence
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31912 Tester/user interface
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Each transistor or logic unit on an integrated circuit wafer is tested prior to interconnect metallization. By means of CAD software, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD computer system. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than with conventional testing at the completed circuit level.

The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure.

Claims

1. A method of making an integrated circuit interconnection comprising the steps of:

forming a conductive film on a substrate;

applying a layer of negative resist over the conductive film;

exposing the negative resist layer with a fixed mask, thereby exposing first portions of the resist layer and leaving second portions of the resist layer unexposed;

exposing a predetermined area of the resist using an optical stepper without a mask, thereby exposing the second portions of the resist layer within said predetermined area;

developing the resist layer; and

etching away the conductive film underlying all unexposed portions of the resist layer.

2. The method of claim 1, further comprising the steps of:

providing a plurality of logic units formed on a surface of the substrate; and

testing the logic units to determine which of the logic units are defective;

wherein the conductive film underlying said predetermined area of the resist layer is associated with interconnection of the defective logic units.

3. The method of claim 2 further comprising the steps of removing any remaining portions of the resist layer and patterning the conductive film in an area corresponding to said predetermined area of the resist layer to form logic unit interconnections that bypass the defective logic units.

4. The method of claim 1, wherein the predetermined area is a rectangle of size less than 100 μ

m by 100 μ

m.

5. The method of claim 1, wherein the predetermined area is less than 1% of a surface area of the substrate.

6. The method of claim 1 further comprising the steps of removing any remaining portions of the resist layer and patterning the conductive film in in area corresponding to said predetermined area of the resist layer.

7. A method of making an integrated circuit interconnection comprising the steps of:

forming a dielectric film on a substrate;

applying a layer of negative resist over the dielectric film;

exposing the negative resist layer with a fixed mask, thereby exposing first portions of the resist layer and leaving second portions of the resist layer unexposed;

exposing a predetermined area of the resist using an optical stepper without a mask, thereby exposing the second portions of the resist layer within said predetermined area;

developing the resist layer; and

etching away the dielectric film underlying all unexposed portions of the resist layer.

8. The method of claim 7, further comprising the steps of:

providing a plurality of logic units formed on a surface of the substrate; and

testing the logic units to determine which of the logic units are defective;

wherein the the conductive film underlying said predetermined area of the resist layer is associated with interconnection of the defective logic units.

9. The method of claim 8 further comprising the steps of removing any remaining portions of the resist layer and patterning the conductive film in an area corresponding to said predetermined area of the resist layer to form logic unit interconnections that bypass the defective logic units.

10. The method of claim 7, wherein the predetermined area is a rectangle of a size less than 100 μ

m by 100 μ

m.

11. The method of claim 7, wherein the predetermined area is less than 1% of a surface area of the substrate.

12. The method of claim 7 further comprising the steps of removing any remaining portions of the resist layer and patterning the conductive film in an area corresponding to said predetermined area of the resist layer.

13. A method of making an integrated circuit interconnection comprising the steps of:

forming a conductive film on a substrate;

applying a layer of positive optical resist over the film;

exposing the resist layer by use of a fixed mask, thereby exposing first portions of the resist layer and leaving second portions of the resist layer unexposed;

exposing a predetermined area of the resist layer by an optical stepper without use of a mask, thereby exposing the second portions of the resist layer within said predetermined area;

developing the resist layer;

etching away the film underlying all of the exposed portions of the resist layer;

removing any remaining portions of the resist layer; and

patterning the film in an area corresponding to said predetermined area.

14. The method of claim 13, further comprising the steps of:

providing a plurality of logic units formed on a surface of the substrate; and

testing the logic units to determine which of the logic units are defective;

wherein said predetermined area of the resist layer is disposed above a portion of the conductive film associated with interconnection of the defective logic units.

15. The method of claim 14 wherein the step of patterning the film within said predetermined area forms logic unit interconnections that bypass the defective logic units.

16. The method of claim 13, wherein the predetermined area is a rectangle of a size less than 100 μ

m by 100 μ

m.

17. The method of claim 13, wherein the predetermined area is less than 1% of a total surface area of the substrate.

18. A method of making an integrated circuit interconnection comprising the steps of:

forming a dielectric film on a substrate;

applying a layer of negative optical resist over the film;

exposing the resist layer by use of a fixed mask, thereby exposing first portions of the resist layer and leaving second portions of the resist layer unexposed;

exposing a predetermined area of the resist layer by an optical stepper without use of a mask, thereby exposing the second portions of the resist layer within said are determined area;

developing the resist layer;

etching away the film underlying all of the non-exposed portions of the resist layer;

removing any remaining portions of the resist layer; and

patterning the film in an area corresponding to said predetermined area.

19. The method of claim 18, further comprising the steps of:

providing a plurality of logic units formed on a surface of the substrate; and

testing the logic units to determine which of the logic units are defective;

and wherein said predetermined area of the resist layer is disposed above a portion of the conductive film associated with interconnection of the defective logic units.

20. The method of claim 19 wherein the step of patterning of the film within said predetermined area forms logic unit interconnections that bypass the defective logic units.

21. The method of claim 18, wherein the predetermined area is a rectangle of a size less than 100 μ

m by 100 μ

m.

22. The method of claim 18, wherein the predetermined area is less than 1% of a total surface area of the substrate.