Clock control technique and system for a microprocessor including a thermal sensor

• US 5,451,892 A
• Filed: 10/03/1994
• Issued: 09/19/1995
• Est. Priority Date: 10/03/1994
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc., The United States of America As Represented By The Secretary of Agriculture
• Original Assignee: Advanced Micro Devices SDN Berhad (Advanced Micro Devices, Inc.)
• Inventors: Bailey, Joseph A.
• Primary Examiner(s): RUBIN, MARGARET R
• Application Number:
  US08/317,719
• Time in Patent Office: 351 Days
• Field of Search: 327/8, 327/47, 327/83, 327/138, 327/291, 327/513, 327/113
• US Class Current: 327/113
• CPC Class Codes: G06F 1/206 comprising thermal management

Abstract

A clock control circuit is provided to control the frequency of a microprocessor clock signal and includes a clock management unit which controls the frequency of a timing signal applied to a clock generator and distribution unit, which correspondingly supplies an internal clock signal to a CPU core of the microprocessor. A thermal sensor is integrated with the semiconductor die which forms the microprocessor circuit. An output signal from the thermal sensor is provided to a primary temperature indicator unit and to an auxiliary temperature indicator unit. The primary temperature indicator unit is configured to assert a primary indicator signal when the temperature of the semiconductor die has increased above a first threshold level referred to as the primary threshold level, and the auxiliary temperature indicator unit is configured to assert an auxiliary indicator signal when the temperature of the semiconductor die exceeds yet a second threshold level referred to as the auxiliary threshold level. The primary and auxiliary threshold levels may be set by writing to a programmable registers unit. The primary and auxiliary temperature indicator unit are associated with hysteresis characteristics whereby, once either indicator signal has been asserted, it will not be deasserted until a hysteresis point is reached.

Claims

1. A microprocessor comprising:

a CPU core capable of executing a predetermined instruction set;

a clock generator and distribution unit coupled to said CPU core, wherein said clock generator and distribution unit is configured to provide a CPU clock signal to said CPU core, and wherein a frequency of said CPU clock signal is dependent upon a frequency of a timing signal; and

a clock control circuit coupled to said clock generator and distribution unit, wherein said clock control circuit includes;

a frequency control circuit configured to selectively vary a frequency of said timing signal depending upon a control signal;

a thermal sensor capable of providing a temperature signal indicative of a temperature associated with said microprocessor;

a primary temperature indicator unit coupled to said thermal sensor, wherein said primary temperature indicator unit is capable of asserting a primary indicator signal if said temperature signal exceeds a first predetermined threshold level;

an auxiliary temperature indicator unit coupled to said thermal sensor and capable of asserting an auxiliary indicator signal if said temperature signal exceeds a second predetermined threshold level; and

a clock management unit coupled to receive said primary indicator signal and said auxiliary indicator signal, and coupled to said frequency control circuit, wherein said clock management unit is configured to vary said control signal to thereby cause a change in the frequency of said timing signal in response to assertions of said primary indicator signal and said auxiliary indicator signal.

2. The microprocessor as recited in claim 1 wherein said primary temperature indicator unit is associated with a hysteresis characteristic whereby, upon assertion of said primary indicator signal, said primary indicator signal remains asserted until said temperature signal has dropped below a first predetermined hysteresis point associated with said primary temperature indicator unit.

3. The microprocessor as recited in claim 2 wherein said auxiliary temperature indicator unit is associated with a hysteresis characteristic whereby, upon assertion of said auxiliary indicator signal, said auxiliary indicator signal remains asserted until said temperature signal has dropped below a second predetermined hysteresis point associated with said auxiliary temperature indicator unit.

4. The microprocessor as recited in claim 1 wherein said clock management unit is configured to control said frequency control circuit such that said timing signal is associated with a first predetermined frequency if said primary indicator signal and said auxiliary indicator signal are asserted, and such that said timing signal is associated with a second predetermined frequency if said auxiliary indicator signal is asserted while said primary indicator signal is deasserted, and such that said timing signal is associated with a third predetermined frequency if said auxiliary indicator signal is deasserted, wherein said first predetermined frequency is lower than said second predetermined frequency, and wherein said second predetermined frequency is lower than said third predetermined frequency.

5. The microprocessor as recited in claim 1 wherein said frequency control circuit includes a phase locked loop circuit coupled to said clock management unit.

6. The microprocessor as recited in claim 5 wherein said phase locked loop circuit generates an output signal which is associated with a predetermined factor of a frequency of an external clock signal provided to said phase locked loop circuit, wherein said timing signal is derived from said output signal.

7. The microprocessor as recited in claim 6 further comprising a divider circuit for receiving said output signal of said phase locked loop circuit and for deriving said timing signal.

8. The microprocessor as recited in claim 1 further comprising a programmable registers unit coupled to said primary temperature indicator unit and to said auxiliary temperature indicator unit, wherein said programmable registers unit is capable of storing said first and second predetermined threshold levels.

9. The microprocessor as recited in claim 8 further comprising a bus coupled to said CPU core and to said programmable registers unit wherein said programmable registers unit may be written via said bus.

10. The microprocessor as recited in claim 1 wherein said temperature signal provided from said thermal sensor is indicative of a temperature of a semiconductor die on which said microprocessor is fabricated.

11. A clock control circuit for providing a timing signal that controls an internal clock frequency of a microprocessor, said clock control circuit comprising:

a frequency control circuit configured to selectively vary a frequency of said timing signal depending upon a control signal;

a thermal sensor capable of providing a temperature signal indicative of a temperature associated with the said microprocessor;

a primary temperature indicator unit coupled to said thermal sensor, wherein said primary temperature indicator unit is capable of asserting a primary indicator signal if said temperature signal exceeds a first predetermined threshold level;

an auxiliary temperature indicator unit coupled to said thermal sensor and capable of asserting an auxiliary indicator signal if said temperature signal exceeds a second predetermined threshold level; and

a clock management unit coupled to receive said primary indicator signal and said auxiliary indicator signal, and coupled to said frequency control circuit, wherein said clock management unit is configured to vary said control signal to thereby cause a change in the frequency of said timing signal in response to assertions of said primary indicator signal and said auxiliary indicator signal.

12. The clock control circuit as recited in claim 11 wherein said primary temperature indicator unit is associated with a hysteresis characteristic whereby, upon assertion of said primary indicator signal, said primary indicator signal remains asserted until said temperature signal has dropped below a first predetermined hysteresis point associated with said primary temperature indicator unit.

13. The clock control circuit as recited in claim 12 wherein said auxiliary temperature indicator unit is associated with a hysteresis characteristic whereby, upon assertion of said auxiliary indicator signal, said auxiliary indicator signal remains asserted until said temperature signal has dropped below a second predetermined hysteresis point associated with said auxiliary temperature indicator unit.

14. The clock control circuit as recited in claim 11 wherein said clock management unit is configured to control said frequency control circuit such that said timing signal is associated with a first predetermined frequency if said primary indicator signal and said auxiliary indicator signal are asserted, and such that said timing signal is associated with a second predetermined frequency if said auxiliary indicator signal is asserted while said primary indicator signal is deasserted, and such that said timing signal is associated with a third predetermined frequency if said auxiliary indicator signal is deasserted, wherein said first predetermined frequency is lower than said second predetermined frequency, and wherein said second predetermined frequency is lower than said third predetermined frequency.

15. The clock control circuit as recited in claim 11 wherein said frequency control circuit includes a phase locked loop circuit coupled to said clock management unit.

16. The clock control circuit as recited in claim 15 wherein said phase locked loop circuit generates an output signal which is associated with a predetermined factor of a frequency of an external clock signal provided to said phase locked loop circuit, wherein said timing signal is derived from said output signal.

17. The clock control circuit as recited in claim 16 further comprising a divider circuit for receiving said output signal of said phase locked loop circuit and deriving said timing signal.

18. A method for controlling a frequency of an internal clock signal which drives a microprocessor comprising the steps of:

generating a temperature signal indicative of a temperature associated with said microprocessor;

comparing said temperature signal with a first predetermined threshold level;

asserting a primary indicator signal if said temperature signal exceeds said first predetermined threshold level;

comparing said temperature signal with a second predetermined threshold level;

asserting an auxiliary indicator signal if said temperature signal exceeds said second predetermined threshold level;

decreasing a frequency of said internal clock signal if said primary indicator signal is asserted; and

increasing said frequency of said internal clock signal if neither said primary indicator signal nor said auxiliary indicator signal are asserted.

19. The method for controlling a frequency of an internal clock signal as recited in claim 18 comprising the further step of programming said first predetermined threshold level and said second predetermined threshold level within a programmable registers unit.

20. The method for controlling a frequency of an internal clock signal as recited in claim 18 comprising the further step of driving said internal clock signal at an intermediate frequency if said auxiliary indicator signal is asserted and said primary indicator signal is deasserted.