Bias circuit and differential amplifier having stabilized output swing

• US 5,451,898 A
• Filed: 11/12/1993
• Issued: 09/19/1995
• Est. Priority Date: 11/12/1993
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Johnson, Mark G.
• Primary Examiner(s): Heyman, John S.
• Assistant Examiner(s): ENGLUND, TERRY LEE
• Application Number:
  US08/151,513
• Time in Patent Office: 676 Days
• Field of Search: 307/491, 307/494, 330/261, 330/253, 330/257, 330/259, 327/563, 327/543, 327/538, 327/519, 327/378, 327/535, 327/65, 327/63, 327/80, 327/82, 327/52, 327/53, 327/54
• US Class Current: 327/563
• CPC Class Codes: H03K 17/145 in field-effect transistor switches
• CPC Class Codes: H03K 5/2481 with at least one differential stage

Abstract

A differential circuit is provided that generates a differential output voltage ΔV that does not vary when the power supply voltage changes and/or when the field effect transistor conductance changes. The bias circuit connected to the differential amplifier stabilizes the output voltage swing ΔV to be insensitive to change in supply voltage and/or transconductance. A feedback loop is provided to drive the voltage to a predetermined voltage dependent upon the threshold voltage of the transistors used (e.g., the threshold voltage of a PMOS transistor). The voltage stabilizes the current source of the differential amplifier via a current mirror coupled to the feedback loop. Therefore, the resultant differential output voltage ΔV is equal to the transistor threshold voltage. As the transistor threshold voltage is independent of the power supply voltage and device transconductance, the differential amplifier output ΔV is stabilized against variations in power supply voltage and transconductance.

Claims

1. A differential amplifier circuit which receives as input a first input voltage and a second input voltage and outputs a differential output voltage indicative of which input voltage is greater, said circuit comprising:

a differential pair of transistors coupled to receive the first input voltage and second input voltage;

first and second load transistors, each load transistor coupled between a first supply voltage and a respective transistor of the differential pair of transistors;

first and second output nodes for providing the differential output voltage, said first output node coupled between a first transistor of the differential pair of transistors and the first load transistor and the second output node coupled between a second transistor of the differential pair of transistors and the second load transistor;

a bias circuit comprising;

a bias load transistor coupled to the first supply voltage, said transistor having gate, first and second nodes, the gate node of the bias load transistor being connected to gate nodes of the first and second load transistors and the first node coupled to the first supply voltage,

a feedback loop coupled to the bias load transistor to maintain a predetermined voltage at said second node of the bias load transistor and a predetermined current through a feedback path loop, said feedback loop maintaining said predetermined voltage at the second node of the bias load transistor independent of variations of said first supply voltage and transconductance of transistors in the circuit, and

a current mirror coupled to receive the current through the feedback path, said current mirror further coupled to the differential pair of transistors to provide a constant current value through said differential pair of transistors;

wherein the differential output is stabilized against variations in supply voltage and transconductance of transistors in the circuit.

2. The differential amplifier circuit as set forth in claim 1, wherein the first and second load transistors and the bias load transistor are of the same size.

3. The differential amplifier circuit as set forth in claim 1, wherein the feedback loop comprises:

a first feedback transistor having gate, first and second nodes, said first node coupled to the first supply voltage and said gate coupled to the second node of the bias load transistor;

a second feedback transistor having gate, first and second nodes, said first node of the second feedback transistor coupled to the second node of the first feedback transistor, said second node of the second feedback transistor coupled to a second supply voltage; and

a third feedback transistor having gate, first and second nodes, said first node of the third feedback transistor coupled to the second node of the bias load transistor, said second node of the third feedback transistor coupled to the current mirror, and the gate node of the third feedback transistor coupled to the first node of the second feedback transistor and the second node of the first feedback transistor.

4. The differential amplifier circuit as set forth in claim 3, wherein the gate node of the second feedback transistor is coupled to the second node of the bias load transistor.

5. The differential amplifier circuit as set forth in claim 3, wherein the gate node of the second feedback transistor is coupled to the first supply voltage.

6. The differential amplifier circuit as set forth in claim 1, wherein the predetermined voltage is equal to difference between the first supply voltage and a threshold voltage of a first feedback loop transistor.

7. The differential amplifier circuit as set forth in claim 1, wherein said current mirror comprises a first current mirror transistor and second current mirror transistor, each transistor having gate, first and second nodes, said gate nodes of each transistor coupled to the first node of the first current mirror transistor, said first node of the first current mirror transistor further coupled to the feedback loop to receive the current, said first node of the second current mirror transistor coupled to the differential pair of transistors, and said second nodes of the first current mirror transistor and second current mirror transistor coupled to a second supply voltage.

8. The differential amplifier circuit as set forth in claim 7, wherein the differential output voltage is adjusted to be a product of a constant and a threshold voltage of a feedback loop transistor, a channel width of said second current mirror transistor being equal to the product of the constant and the channel width of the first current mirror transistor.

9. The differential amplifier circuit as set forth in claim 7, wherein the differential output voltage is adjusted to be a product of a constant and a threshold voltage of a feedback loop transistor, a channel width of said bias load transistor being equal to the product of the constant and the channel width of the second load transistor of the differential pair of transistors.

10. The differential amplifier circuit as set forth in claim 1, wherein the feedback loop comprises:

a first feedback transistor having gate, first and second nodes, said first node of the first feedback transistor coupled to the first supply voltage and said gate node of the first feedback transistor coupled to the second node of the bias load transistor;

a resistor coupled between a second supply voltage and the second node of the first feedback transistor; and

a second feedback transistor having gate, first and second nodes, said first node of the second feedback transistor coupled to the second node of the bias load transistor, said second node of the second feedback transistor coupled to the current mirror, and the gate node of the second feedback transistor coupled the second node of the first feedback transistor.

11. The differential amplifier as set forth in claim 10, wherein the resistor is of a value of at least 10⁴ ohms.

12. The differential amplifier circuit as set forth in claim 1, wherein the said first supply voltage is equal to a potential greater than ground.

13. The differential amplifier circuit as set forth in claim 12, wherein the first node of a transistor is a source node and the second node of a transistor is a drain node.

14. The differential amplifier circuit as set forth in claim 3, wherein the second supply voltage equals a ground potential, said first supply voltage is equal to a potential greater than ground, the first node of a transistor is a source node and the second node of a transistor is a drain node.

15. The differential amplifier circuit as set forth in claim 7, wherein the second supply voltage equals a ground potential, said first supply voltage is equal to a potential greater than ground, the first node of a transistor is a source node and the second node of a transistor is a drain node.

16. The differential amplifier circuit as set forth in claim 10, wherein the second supply voltage equals a ground potential, said first supply voltage is equal to a potential greater than ground, the first node of a transistor is a source node and the second node of a transistor is a drain node.

17. The differential amplifier circuit as set forth in claim 1, wherein the said first supply voltage is equal to a potential equal to ground.

18. The differential amplifier circuit as set forth in claim 17, wherein the first node of a transistor is a drain node and the second node of a transistor is a source node.

19. The differential amplifier circuit as set forth in claim 3, wherein the first supply voltage equals a ground potential, said second supply voltage is equal to a potential greater than ground, the first node of a transistor is a drain node and the second node of a transistor is a source node.

20. The differential amplifier circuit as set forth in claim 7, wherein the first supply voltage equals a ground potential, the first node of a transistor is a drain node and the second node of a transistor is a source node.

21. The differential amplifier circuit as set forth in claim 10, wherein the first supply voltage equals a ground potential, the first node of a transistor is a drain node and the second node of a transistor is a source node.

22. In a differential amplifier circuit comprising a pair of amplifier transistors having load transistors, said circuit receives as input a first input voltage and a second input voltage and outputs a differential output voltage indicative of which input voltage is greater, a bias circuit that stabilizes the differential output against variations in a first supply voltage and transistor transconductance, said bias circuit comprising:

a bias load transistor approximately equal in size to sizes of the load transistors, a gate node of the bias load transistor coupled to gate nodes of the load transistors;

a feedback loop to maintain a predetermined voltage at a first node of the bias load transistor and a current through a feedback path, said feedback loop maintaining said predetermined voltage at the first node of the bias load transistor independent of variations of said first supply voltage and transconductance of transistors in the circuit, and

a current mirror coupled to the feedback loop to receive the current through the feedback path, said current mirror further coupled to the differential pair of transistors to provide a constant current value through said differential pair of transistors;

wherein the differential output is stabilized against variations in said first supply voltage and transistor transconductance.

23. The bias circuit as set forth in claim 22, wherein a source node of the bias load is coupled to the first supply voltage.

24. The bias circuit as set forth in claim 22, wherein a drain node of the bias load is coupled to a second supply voltage.

25. The bias circuit as set forth in claim 22, wherein a drain node of the bias load is coupled to a supply voltage equal to ground potential.

26. The bias circuit as set forth in claim 22, wherein a source node of the bias load is coupled to a supply voltage at a potential greater than ground potential.

27. The differential amplifier circuit as set forth in claim 23, wherein the feedback loop comprises:

a first feedback transistor having a gate, drain and source node, said source node of the first feedback transistor coupled to the supply voltage and said gate node of the first feedback transistor coupled to a drain node of the bias load transistor;

a second feedback transistor having a gate, drain and source node, said source node of the second feedback transistor coupled to the drain node of the first feedback transistor, said drain node of the second feedback transistor coupled to a ground; and

a third feedback transistor having a gate, drain and source node, said source node of the third feedback transistor coupled to the drain of the bias load transistor, said drain node of the third feedback transistor coupled to the current mirror, and the gate node of the third feedback transistor coupled to the source node of the second feedback transistor and the drain node of the first feedback transistor.

28. The differential amplifier circuit as set forth in claim 23, wherein the feedback loop comprises:

a first feedback transistor having a gate, drain and source node, said source node of the first feedback transistor coupled to the supply voltage and said gate node of the first feedback transistor coupled to a drain node of the bias load transistor;

a resistor coupled between ground and the drain node of the first feedback transistor; and

a second feedback transistor having a gate, drain and source node, said source node of the second feedback transistor coupled to the drain node of the bias load transistor, said drain node of the second feedback transistor coupled to the current mirror, and the gate node of the second feedback transistor coupled to the resistor and the drain node of the first feedback transistor.

29. The differential amplifier circuit as set forth in claim 24, wherein the feedback loop comprises:

a first feedback transistor having a gate, drain and source node, said drain node of the first feedback transistor coupled to the ground and said gate node of the first feedback transistor coupled to the source node of the bias load transistor;

a second feedback transistor having a gate, drain and source node, said drain node of the second feedback transistor coupled to the source node of the first feedback transistor, said source node of the second feedback transistor coupled to said first supply voltage; and

a third feedback transistor having a gate, drain and source node, said drain node of the third feedback transistor coupled to the source of the bias load transistor, said source node of the third feedback transistor coupled to the current mirror, and the gate node of the third feedback transistor coupled to the drain node of the second feedback transistor and the source node of the first feedback transistor.

30. The differential amplifier circuit as set forth in claim 22, wherein said current mirror comprises a first current mirror transistor and second current mirror transistor, each transistor having a gate, first and second node, said gate nodes of each transistor coupled to the first node of the first transistor, said first node of the first transistor further coupled to the feedback loop to receive the current, said first node of the second current mirror transistor coupled to the differential pair of transistors, said second nodes coupled to a first potential.

31. The differential amplifier circuit as set forth in claim 30, wherein the differential output voltage is adjusted to be a product of a constant and a threshold voltage of a feedback loop transistor, a channel width of said second current mirror transistor being equal to the product of the constant and the channel width of the first current mirror transistor.

32. The differential amplifier circuit as set forth in claim 30, wherein the differential output voltage is adjusted to be a product of a constant and a threshold voltage of a feedback loop transistor, a channel width of said bias load transistor being equal to the product of the constant and the channel width of a second load transistor of the differential pair of transistors.

33. In a differential amplifier circuit comprising a pair of amplifier transistors having load transistors, said circuit receives as input a first input voltage and a second input voltage and outputs a differential output voltage indicative of which input voltage is greater, a method for biasing the circuit that stabilizes the differential output against variations in supply voltage and transistor transconductance, said method comprising the steps of:

connecting a bias load transistor to the load transistors, said bias load transistor approximately equal in size to sizes of the load transistors, a gate node of the bias load transistor coupled to gate nodes of the load transistors;

maintaining a predetermined voltage at a first node of the bias load transistor and a current through a feedback path, said feedback loop maintaining said predetermined voltage at the first node of the bias load transistor independent of variations of said supply voltage and transconductance of transistors in the circuit, and

mirroring the current to the pair of amplifier transistors to provide a constant current value through said pair of amplifier transistors;

wherein the differential output is stabilized against variations in said supply voltage and transistor transconductance.